Strengthen Anti-ESD Characteristics in an HV LDMOS With Superjunction Structures

TLDR: In this article, an embedded superjunction (SJ) device under tests (DUTs) of 45-V HV n-channel lateral-diffused MOS (nLDMOS) is developed, which offer a low on-resistance as compared with the traditional nLDMos due to the redistribution of electric field or/and higher doping density in the drain side.

Abstract: In general, the antielectrostatic discharge (ESD) ability of a high voltage (HV) MOSFET device will be very low if it is not optimized through the addition of reliability engineering. Accordingly, in this paper, some embedded superjunction (SJ) device under tests (DUTs) of 45-V HV n-channel lateral-diffused MOS (nLDMOS) are developed, which offer a low on-resistance as compared with the traditional nLDMOS due to the redistribution of electric field or/and higher doping density in the drain side. In order to evaluate how various physical parameters affect the anti-ESD capability, these DUTs will change the widths and shapes of the P/N pillars. From the testing results, it can be found that the I t2 values of SJ-nLDMOS DUTs will be higher than that of a traditional nLDMOS, while the equivalent immunity level is even greater than HBM 10 kV. In this paper, the I t2 values of developed SJ-nLDMOS DUTs were increased at least by 109%, 31%, and 159% over that of the traditional nLDMOS for the Types 1-3 embedded SJ, respectively. Moreover, in some geometry architectures of an SJ-LDMOS, the holding voltage can be greater than the traditional nLDMOS. Therefore, by considering the relationships between these three kinds of SJ-nLDMOS DUTs and the I t2 values, it can be determined that the SJ structure is good for ESD/latch-up immunities especially for the ESD reliability.