Journal ArticleDOI
A Review on the ESD Robustness of Drain-Extended MOS Devices
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TLDR
In this article, the limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes.Abstract:
This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.read more
Citations
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Journal ArticleDOI
ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC
Chia-Tsen Dai,Ming-Dou Ker +1 more
TL;DR: In this paper, an area-efficient ESD protection design with stacked high-holding-voltage silicon-controlled rectifier (HHVSCR) is proposed and verified in a 0.25- $\mu \text{m}$ 5/60 V Bipolar-CMOS-DMOS process.
Journal ArticleDOI
Part I: On the Unification of Physics of Quasi-Saturation in LDMOS Devices
TL;DR: In this paper, a unified theory to explain physics of quasi-saturation behavior in laterally diffused MOS (LDMOS) devices is presented, which covers all voltage-current-temperature trends.
Journal ArticleDOI
A Novel Drain Design for ESD Improvement of UHV-LDMOS
TL;DR: In this paper, a drain design with small multidiffusions is proposed to eliminate the current crowding and to enhance its ESD performance, which is shown to improve the performance.
Proceedings ArticleDOI
Trap assisted avalanche instability and safe operating area concerns in AlGaN/GaN HEMTs
Bhawani Shankar,Ankit Soni,Manikant Singh,Rohith Soman,Hareesh Chandrasekar,Nagaboopathy Mohan,Neha Mohta,Nayana Ramesh,Shreesha Prabhu,Abhay Kulkarni,Digbijoy N. Nath,Rangarajan Muralidharan,K. N. Bhat,Srinivasan Raghavan,Navakant Bhat,Mayank Shrivastava +15 more
TL;DR: In this paper, the authors reported the very first systematic study on the physics of avalanche instability and SOA concerns in AlGaN/GaN HEMTs using sub-μs pulse characterization, post stress degradation analysis, well calibrated TCAD simulations and failure analysis by SEM and TEM.
Journal ArticleDOI
Design, fabrication and test of novel LDMOS-SCR for improving holding voltage
TL;DR: In this paper, a novel structure called GateDot was proposed to improve the holding voltage by inserting P+ slots into the polygate of traditional LDMOS-SCR.
References
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Journal ArticleDOI
A theory of transistor cutoff frequency (f T ) falloff at high current densities
TL;DR: In this paper, it was shown that the observed falloff in the f T of a transistor at high currents is due to the spreading of the neutral base layer into the collector region of the device at high current densities.
Journal ArticleDOI
Screening of hot-carrier relaxation in highly photoexcited semiconductors
TL;DR: In this paper, the carrier density dependence of the hot-carrier energy relaxation rate in highly photoexcited semiconductors is investigated, and the results indicate important differences between polar direct-gap and nonpolar indirect-gap materials.
Journal ArticleDOI
Analysis of lateral DMOS power devices under ESD stress conditions
Markus Paul Josef Mergens,Wolfgang Wilkening,S. Mettler,Heinrich Wolf,A. Stricker,Wolfgang Fichtner +5 more
TL;DR: In this paper, the physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated in detail by transmission line pulse (TLP) measurements, human body model (HBM) testing, emission microscopy (EMMI) experiments, and two-dimensional (2-D) device simulations.
Journal ArticleDOI
High-voltage drain extended MOS transistors for 0.18-/spl mu/m logic CMOS process
Jozef C. Mitros,Chin-Yu Tsai,Hisashi Shichijo,M. Kunz,Alec J. Morton,D. Goodpaster,Dan M. Mosher,Taylor R. Efland +7 more
TL;DR: In this paper, complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology.
Proceedings ArticleDOI
Lateral DMOS design for ESD robustness
TL;DR: In this paper, the authors present the design of efficient ESD protection in lateral DMOS (LDMOS) power transistor, using characterization of the LDMOS transistor under ESD conditions with various gate and drain clamps, the design for minimum power dissipation is established.
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