Patent
Thin film transistor with three dimensional multichannel structure
TLDR
In this paper, a three-dimensional multichannel structure of a thin-film transistor gate with a 3D multi-channel structure is described, where the source/drain electrodes are formed so as to be spaced from and opposite to each other on a substrate, and the whole outer layer of each sub-semiconductive layer is used as channel regions.Abstract:
A thin film transistor gate structure with a three-dimensional multichannel structure is disclosed. The thin film transistor gate structure according to the present invention comprises source/drain electrodes formed so as to be spaced from and opposite to each other on a substrate; semiconductive layers, comprised of a plurality of sub-semiconductive layers, each formed in a row, each end of the sub-semiconductive layers being in ohmic-contact with the source/drain electrodes; gate insulating layers surrounding each of the semiconductive layers; and gate electrodes surrounding each of the gate insulating layers. Accordingly, the whole outerlayers of each sub-semiconductive layer surrounded by the gate electrodes serve as channel regions. As a result, the effective channel area increases, thereby improving the channel conductance and current driving ability.read more
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References
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Patent
MIS transistor structure for increasing conductance between source and drain regions
TL;DR: A metal-insulator-semiconductor transistor comprises an insulator layer, a semiconductor body, a gate electrode of a conductive material provided in contact with the gate insulator film so as to cover the channel region underneath the gate, except for the part of the channel regions in contact as mentioned in this paper.
Journal ArticleDOI
Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits
Akihiro Nitayama,Hiroshi Takato,Naoko Okabe,Kazumasa Sunouchi,Katsuhiko Hieda,Fumio Horiguchi,F. Masuoka +6 more
TL;DR: The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically as mentioned in this paper, and the gate electrode surrounds the crowded multipillar silicon islands.
Patent
Thin film MOS transistor having pair of gate electrodes opposing across semiconductor layer
Hisao Hayashi,Michio Negishi,Takashi Noguchi,Takefumi Ohshima,Yuji Hayashi,Toshikazu Maekawa,Takeshi Matsushita +6 more
TL;DR: In this article, a thin-film MOS transistor has a construction which can minimize scattering of electron and thus maximize electrons mobility for allowing higher speed operation of the transistor, which can be seen as a way of maximizing the electron mobility.
Journal ArticleDOI
Polysilicon encapsulated local oxidation
TL;DR: Polysilicon encapsulated local oxidation (PELOX) was proposed as an effective isolation technique that satisfied advanced device requirements without any difficult-to-control structures or processes as mentioned in this paper, and simple modifications to a standard local oxidation of silicon (LOCOS) process flow minimize encroachment without introducing defects.
Journal ArticleDOI
High-voltage poly-Si TFTs with multichannel structure
TL;DR: In this article, the authors used a nonsymmetric offset gate structure between the source and the gate (L/sub OFF, 1/)/2) and between the gate and the drain (l/sub Off, 2/2)/3/4) to achieve high-voltage (>100-V) and large-transconductance poly-Si thin-film transistors.
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