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Open accessProceedings ArticleDOI
Eyal En Gad, Anxiao Jiang, Jehoshua Bruck 
01 Jul 2012
23 Citations
Since capacity can be achieved only with cells that have a large number of levels, we propose a new architecture that consists of multi-cells - each an aggregation of a number of floating gate transistors.
The simulation results suggest that the hybrid 7/3 counter and 7|2 compressor, designed in 0.25 /spl mu/m CMOS, achieve between 53% and 61% higher speed when compared with traditional Boolean logic and threshold logic counterparts, at the expense of between 67% and 74% more transistors.
Proceedings ArticleDOI
25 Mar 2008
7 Citations
This allows a reduction on the number of needed transistors to implement a circuit.
The new transistors have superior analog performance compared to the standard logic devices resulting in significant area savings and greater analog functionality.
The proposed structures reduce the number of the transistors considerably and have very high driving capability.
Journal ArticleDOI
L. F. Eastman, Umesh K. Mishra 
01 May 2002-IEEE Spectrum
234 Citations
These same characteristics of speed, high-power handling, and heat resistance would also suit the transistors for many other uses.
FinFET CMOS is a viable candidate, offering high-density and low-leakage digital transistors.
Two transistors next to each other on the chip with exactly the same geometries and strain distributions may have characteristics from each end of a wide statistical distribution.

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