Showing papers on "Analog-to-digital converter published in 2011"

Xampling: Analog to digital at sub-Nyquist rates

Abstract: The authors present a sub-Nyquist analog-to-digital converter of wideband inputs. The circuit realises the recently proposed modulated wideband converter, which is a flexible platform for sampling signals according to their actual bandwidth occupation. The theoretical work enables, for example, a sub-Nyquist wideband communication receiver, which has no prior information on the transmitter carrier positions. The present design supports input signals with 2 GHz Nyquist rate and 120 MHz spectrum occupancy, with arbitrary transmission frequencies. The sampling rate is as low as 280 MHz. To the best of the authors' knowledge, this is the first reported hardware that performs sub-Nyquist sampling and reconstruction of wideband signals. The authors describe the various circuit design considerations, with an emphasis on the non-ordinary challenges the converter introduces: mixing a signal with a multiple set of sinusoids, rather than a single local oscillator, and generation of highly transient periodic waveforms, with transient intervals on the order of the Nyquist rate. Hardware experiments validate the design and demonstrate sub-Nyquist sampling and signal reconstruction.

A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration

Abstract: This paper presents a sub-radix-2 redundant architecture to improve the performance of switched-capacitor successive-approximation-register (SAR) analog-to-digital converters (ADCs). The redundancy not only guarantees digitally correctable static nonlinearities of the converter, it also offers means to combat dynamic errors in the conversion process, and thus, accelerating the speed of the SAR architecture. A perturbation-based digital calibration technique is also described that closely couples with the architecture choice to accomplish simultaneous identification of multiple capacitor mismatch errors of the ADC, enabling the downsizing of all sampling capacitors to save power and silicon area. A 12-bit prototype measured a Nyquist 70.1-dB signal-to-noise-plus-distortion ratio (SNDR) and a Nyquist 90.3-dB spurious free dynamic range (SFDR) at 22.5 MS/s, while dissipating 3.0-mW power from a 1.2-V supply and occupying 0.06-mm2 silicon area in a 0.13-μm CMOS process. The figure of merit (FoM) of this ADC is 51.3 fJ/step measured at 22.5 MS/s and 36.7 fJ/step at 45 MS/s.

A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS

Abstract: This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register (SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. The sampling front-end consists of four interleaved T/Hs at 650 MS/s that are optimized for timing accuracy and sampling linearity, while the back-end consists of four ADC arrays, each consisting of 16 10b current-mode non-binary SAR ADCs. The interleaving hierarchy allows for many ADCs to be used per T/H and eliminates distortion stemming from open loop buffers interfacing between the front-end and back-end. Startup on-chip calibration deals with offset and gain mismatches as well as DAC linearity. Measurements show that the prototype ADC achieves an SNDR of 48.5 dB and a THD of less than 58 dB at Nyquist with an input signal of 1.4 . An estimated sampling clock skew spread of 400 fs is achieved by careful design and layout. Up to 4 GHz an SNR of more than 49 dB has been measured, enabled by the less than 110 fs rms clock jitter. The ADC consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm.

A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface

Abstract: This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 μm CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 μW at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 f J/conversion-step.

An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications

Abstract: An adaptive resolution (AR) asynchronous analog-to-digital converter (ADC) architecture is presented. Data compression is achieved by the inherent signal dependent sampling rate of the asynchronous architecture. An AR algorithm automatically varies the ADC quantizer resolution based on the rate of change of the input. This overcomes the trade-off between dynamic range and input bandwidth typically seen in asynchronous ADCs. A prototype ADC fabricated in a 0.18 μm CMOS technology, and utilizing the subthreshold region of operation, achieves an equivalent maximum sampling rate of 50 kS/s, an SNDR of 43.2 dB, and consumes 25 μW from a 0.7 V supply. The ADC is also shown to provide data compression for accelerometer applications as a proof of concept demonstration.

A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS

Abstract: This paper presents a new very low-power, low-voltage successive approximation analog to digital converter (SAR ADC) design based on supply boosting technique. The supply boosting technique (SBT) and supply boosted (SB) circuits including level shifter, comparator, and supporting electronics are described. Supply boosting provides wide input common mode range and sub-1 Volt operation for the circuits designed in standard CMOS processes that have only high-Vt MOSFETs. A 10-bit supply boosted SAR ADC was designed and fabricated in a standard 0.5 μm, 5 V, 2P3M, CMOS process in which threshold voltages of NMOS and PMOS devices are +0.8 and ?0.9 V, respectively. Fabricated SB-SAR ADC achieves effective number of bits (ENOB) of 8.04, power consumption of 147 nW with sampling rate of 1.0 KS/s on 1 Volt supply. Measured figure of merit (FOM) was 280 fJ/conversion-step. Proposed supply boosting technique improves input common mode range of both SB comparator and SAR ADC, allows sub-1 Volt operation when threshold voltages are in the order of the supply voltage, and achieves low energy operation. Thus, SBT is suitable for mixed-signal circuit designed for energy limited applications and systems in where supply voltage is in the order of threshold voltages of the process.

A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS

Abstract: A delay-line-based analog-to-digital converter for high-speed applications is introduced. The ADC converts the sampled input voltage to a delay that controls the propagation velocity of a digital pulse. The output digital code is generated based on the propagation length of the pulse in a fixed time window. The effects of quantization noise, jitter, and mismatch are discussed. We show that because of the averaging mechanism of the delay-line, this structure is more power efficient in the presence of noise and mismatch in deep sub-micron CMOS. To show the feasibility of this approach, a 4 bit 1.2 GS/s ADC is designed and fabricated in 65 nm CMOS in an active area of 110 μm × 105 μm. The measured INL and DNL of the ADC are below 0.8 bits and 0.5 bits and it achieves an SNDR of 20.4 dB at Nyquist rate. This delay-line-based ADC consumes 2 mW of power from a 1.2 V supply resulting in 196 fJ/conversion step without using any calibration or post-processing.

Two-stage analog-to-digital converter using sar and tdc

Abstract: Various embodiments of this disclosure may describe a two-stage ADC circuit, and a time-interleaved system based on the two-stage ADC circuit. The two-stage ADC circuit may include a SAR converter for the first stage and a charge based TDC for the second stage. The two-stage ADC circuit may be used in high performance serial I/O applications. Other embodiments may be disclosed and claimed.

Solid-state imaging apparatus

Abstract: A solid-state imaging apparatus comprising a plurality of pixels generating a photoelectric conversion signal, a column amplifying unit corresponding to columns of the pixels, for outputting a first and second signals generated by amplifying the photoelectric conversion signal at a smaller first gain and larger second gain respectively, an analog to digital converter ( 21 ) for converting the first and second signals from an analog signal to a digital signal, a comparing unit ( 224 ) for inputting the digital signal from the analog to digital converter, level-shifting into the same gain level the first and second signals converted by the analog to digital converter, and thereafter detecting a gain error between the level-shifted first and second signals, and a correction unit ( 226 ) for correcting the first and second signals based on the gain error.

Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter

Abstract: A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.

A new approach to design low power cmos flash a/d converter

Abstract: In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.

Design and Characteristics of a Multichannel Front-End ASIC Using Current-Mode CSA for Small-Animal PET Imaging

Abstract: This paper presents the design and characteristics of a front-end readout application-specific integrated circuit (ASIC) dedicated to a multichannel-plate photodetector coupled to LYSO scintillating crystals. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. A current-mode charge-sensitive amplifier is proposed for this application. This paper presents performance characteristics of a 10-channel prototype chip designed and fabricated in a 0.35-μm complementary metal-oxide semiconductor process. The main results of simulations and measurements are presented and discussed. The gain of the chip is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The signal-to-noise ratio is 39 dB and the rms noise is 300 μV/√(Hz). The nonlinearity is less than 3% and the crosstalk is about 0.2%. The power dissipation is less than 15 mW/channel. This prototype will be extended to a 64-channel circuit with integrated time-to-digital converter and analog-to-digital converter together for a high-sensitive small-animal positron emission tomography imaging system.

A low-noise clockless simultaneous 32-channel wireless neural recording system with adjustable resolution

Abstract: We present a 32-channel wireless implantable neural recording (WINeR-5) system-on-a-chip (SoC) that operates based on time division multiplexing (TDM) of pulse width modulated (PWM) samples, similar to a single-slope analog to digital converter (ADC) that is made wireless. By transmitting a TDM---PWM signal, we have relaxed the need for wide bandwidth and accurate timing between transmitter and receiver units, which is necessary in wideband digital wireless links. The WINeR-5 system uses FSK modulation scheme with RF carrier at 898/926 MHz. The baseband TDM---PWM signal bandwidth is 18 MHz, which is also the bandwidth of the receiver baseband low-pass filter. Further, by moving the digitization circuitry outside the body, we have reduced the size, complexity, and power consumption of the implantable unit. A clockless asynchronous design has been utilized to manage TDM switching times such that no switching occurs during sensitive PWM onsets. Control over sampling rate, dynamic range, and resolution provides the user with tradeoffs that can optimize the system performance for the intended application. The SoC has been implemented in a 0.5-μm standard CMOS process, measuring 3.3 × 3 mm2 and consuming 5.6 mW at ±1.5 V when all channels are active. Measured input referred noise for the entire system, including the receiver at 1 m distance, is 4.9 μVrms in 1 Hz---8.8 kHz range. Functionality of the WINeR-5 system has also been demonstrated in acute in vivo experiments.

Photonic Time-Stretched Analog-to-Digital Converter Amenable to Continuous-Time Operation Based on Polarization Modulation With Balanced Detection Scheme

Abstract: In this paper, we show analytically and experimentally that a polarization modulator which supports TE and TM modes of opposite phase modulation indexes can be utilized to reject dispersion-induced even-order distortions in a photonic Time-Stretched Analog-to-Digital Converter (TS-ADC). The output of the polarization modulator propagates through a single dispersive channel. This makes the present scheme amenable to continuous operation. Based on the virtual time gating principle, the continuous-time RF signal is time-stretched by a factor of 4 and segmented into four channels prior to digitization. For a single channel, differential operation is achieved by using a polarization beam-splitter that generates complementary pulses which are fed to a balanced detector. The differential operation helps to reject dispersion-induced even-order distortions and the balanced detection assists in the suppression of second-order distortion as well as improving the signal-to-noise ratio (SNR) by 6 dB. Using a 10 bit electronic ADC with a sampling rate of 2 GSamples/s, we demonstrate digitization of RF signals up to a frequency of 950 MHz and obtain ~ 3.56 effective number of bits (ENOB) with a single channel at ~ 31.6% of the electronic ADC's peak-to-peak full scale voltage. With adequate backend digitizing hardware, a four-channel continuous-time TS-ADC with a sampling rate of 8 GSamples/s can be realized to handle RF frequencies as high as 4 GHz.

Calibration of impairments in a multichannel time-interleaved adc

Abstract: Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC) A number, M, of clock signals drive a corresponding number of main ADC elements with a selected plurality of different clock phases Each of the ADCs has at least one of an offset correction input, a gain correction input, or a phase correction input The M digital values output by the ADCs are interleaved to form a digital representation of the input signal Also provided is a reference ADC that outputs reference digital values in response to at least one of the M clock signals at a time The output of the reference ADC is compared and/or combined with the output from a selected one of the main ADCs to provide an estimate of offset, gain or phase The error is accumulated to determine a corresponding correction of offset, gain or phase which is then fed back to the respective input of the corresponding main ADC

Digital lightning detection method and device thereof

Abstract: The invention relates to a digital lightning detection method and a device thereof. The method comprises the following steps: receiving an electromagnetic signal generated when cloud-to-ground flash lightning discharging to generate an electric detection signal; digitalizing the conditioned electric detection signal; filtering the digital signal; establishing a uniform time scale; establishing a lightning signal identification criterion and a digitized cloud-to-ground flash lightning signal identification model by a time determination method, a bipolar test method and a homopolar test method by considering transmission features of a lightning electromagnetic radiation waveform; establishing a time window preprocessing area, and acquiring a development trend of the input digital signal andthe corresponding typical parameters; and computing and determining the parameters of the input digital signal in combination with data in the time window by the digitized cloud-to-ground flash lightning signal identification model . The device consists of an antenna, a signal conditioner, an analog to digital converter, a module of cloud-to-ground flash lightning signal identification model, a system control manager, an assistant control manager, a communication interface, an external memory and a clock.

An ultra-low-power SAR ADC with an area-efficient DAC architecture

Abstract: An ultra-low-power area-efficient 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve ultra-low-power performance a DAC architecture is proposed that employs two rail-to-rail low-power unity-gain buffers and only 4 minimum-size capacitors instead of the conventional binary-weighted capacitor array. Thereby, power consumption and area are drastically reduced by virtue of lower switching activity and smaller size capacitor array. The proposed 8-bit SAR ADC is designed and simulated in a 0.13µm CMOS process. Simulation results show that for a 2.4 kHz (12.4 kHz) input signal while sampling at 25 kHz, the ADC achieves an ENOB of 7.9 (7.8), consumes 290 nW (350 nW) form a 0.8 V analog supply and a 0.6 V digital supply, and achieves a FoM of 48 fJ/conversion-step (62 fJ/conversion-step).

Analog to digital converter circuit

Abstract: The present invention provides a pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) circuit with decoupled flip-around MDAC, capacitive attenuation solution and self-embedded offset cancellation. The flip-around MDAC architecture is built for low inter-stage gain implementation. A capacitive attenuation solution is provided for minimizing the power dissipation and optimizing conversion speed. The design reuses SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time.

Analog-to-digital converter and correction method thereof

Abstract: An analog-to-digital (AD) converter device, includes: a capacitive digital-to-analog converter (DAC) including a reference capacitor group having capacitors which are weighted with a ratio, one terminal of each of the capacitors being coupled to a common signal line, the other terminal of each of the capacitors being coupled to one of reference power supplies via one of switches; a comparator to compare a voltage of the common signal line with a reference voltage; a successive approximation routine circuit to control the switches based on a comparison result of the comparator; an offset correction circuit to correct an offset of the comparator; and a DAC correction circuit to correct an error in a voltage change of the common signal line, the offset correction circuit and the DAC correction circuit performing a correction so that a residual offset of the comparator and a residual error of the capacitive DAC cancel.

RF Front-End Concept and Implementation for Direct Sampling of Multiband Signals

Abstract: The placement of the analog-to-digital converter as near the antenna as possible is a key issue in the software-defined radio receiver design. Direct sampling of the incoming filtered signal is a compact solution enabling channel simultaneity. In this brief, in the context of evenly spaced equal-bandwidth multiband systems, sufficient conditions for the channel allocation assuring that the minimum sub-Nyquist sampling frequency does not imply aliasing are provided. Subsequently, as a validation example, the design of a minimum-sampling-frequency acquisition system for quad-band applications within a ultrawideband frequency range is shown. Moreover, an innovative solution for its radio-frequency front end, basically consisting of a signal-interference multiband bandpass filter, is reported. Experimental results of the built microstrip-filter prototype for the proposed 1-3-GHz-range quad-band system are also given.

Pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration

Abstract: The invention discloses a pipelined analog-digital converter (ADC) capable of carrying out background digital calibration. The pipelined (ADC) comprises a sampling hold circuit, M calibrated level circuit modules, N level circuit modules and a back level analog-to-digital conversion module which are sequentially connected in series, wherein each calibrated level circuit module is connected with a corresponding digital calibrated level circuit; the quantized value output port of the level circuit module and the quantized value output port of a back level analog-to-digital conversion module are respectively connected with a time delay and dislocation summation module; and the output end of the time delay and dislocation summation module is sequentially and reversely connected in series in the digital calibrated level circuit. The pipelined analog-to-digital converter provided by the invention has the advantages that the thinking is inventive, the analog circuit has a simple structure, a pseudo random number generator and a multi-way selection switch are additionally arranged on the foundation of the existing technical structure, and the working of other analog circuits can not be unaffected in the working process; and simultaneously, the principle of the digital circuit segment is simple and is easy to realize, the error of the pipelined ADC can be reduced obviously, the linearity of the pipelined ADC can be improved, and the dynamic properties of the pipelined ADC can be improved.

Quantization circuit having VCO-based quantizer compensated in phase domain and related quantization method and continuous-time delta-sigma analog-to-digital converter

Abstract: A quantization circuit includes a quantizer and a compensation circuit. The quantizer includes a voltage-to-phase converter and a phase difference digitization block. The voltage-to-phase converter is arranged for generating a phase signal according to an input voltage. The phase difference digitization block is arranged for generating a quantization output according to a phase difference between a phase of the phase signal and a reference phase input. The compensation circuit is arranged for applying compensation to the phase difference digitization block according to the quantization output.

Conversion and calibration algorithm for improving output signal-to-noise ratio of successive approximation (SAR) analog-to-digital converter (ADC) and ADC

Abstract: The invention provides a conversion and calibration algorithm for improving output signal-to-noise ratio of a successive approximation (SAR) analog-to-digital converter (ADC) and the ADC. By adopting the algorithm, the overall output signal-to-noise ratio of the ADC can be effectively improved through a calibration algorithm and the ADC on the premise of not changing equivalent input noise of a comparator in the SAR ADC. In the technical scheme, the last least significant bit (LSB) cell capacitance Cc connected at a fixed potential in the traditional binary-weighted digital-to-analog converter (DAC) capacitance array is taken as the DAC capacitance of an additional period; and a comparison operation is carried out once again after the original SAR ADC comparison period is completed, and then the original ADC quantized result output is calibrated according to the obtained comparison result, thus improving the overall output signal-to-noise ratio of the ADC in the statistical sense.

Subrange analog-to-digital converter and method thereof

Abstract: The configurations and adjusting method of a subrange analog-to-digital converter (ADC) are provided. The provided subrange ADC includes a X.5-bit flash ADC, a Y-bit SAR ADC and a (X+Y)-bit segmented capacitive digital-to-analog converter (DAC).

Successive approximation register analog-to-digital converter and analog-to-digital conversion method using the same

Abstract: A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) includes a Sample-and-Hold Amplifier (SHA) for sampling and holding an externally input analog voltage, a comparator for comparing a level of the sampled and held analog voltage with a level of an analog signal corresponding to n bits and generating a comparison signal according to result of comparison, an SAR logic circuit for sequentially generating a digital signal from a Most significant Bit (MSB) to a Least Significant Bit (LSB) in response to the comparison signal, a Digital-to-Analog Converter (DAC) for providing the analog signal to the comparator, and an output register for holding the sequentially generated digital signal from the MSB to the LSB to generate an n-bit digital signal, wherein, upon externally receiving a start signal, the SAR logic circuit generates a digital signal of a MSB having a one-bit phase delay compared with the start signal.

High Accuracy And High Dynamic Range MEMS Inertial Measurement Unit With Automatic Dynamic Range Control

Abstract: Embodiments relate to a MEMS IMU having an automatic gain control. The dynamic measurement range of the MEMS IMU is controlled by controlling the gain of a signal amplifier before the analog to digital converter (ADC) to make full use of the ADC range. In one embodiment, two or more MEMS inertial sensor sets are installed in the IMU. One of the sensor sets is for high accuracy with low dynamic range, and the other set or sets is for higher dynamic range with less resolution or accuracy. In one implementation, a digital processor determines which of the sensor sets to be used according to the system dynamic estimation. In another implementation, the system weights the sensor outputs from the sensor sets according to the system dynamics.

Successive approximation analog-to-digital converter having auxiliary prediction circuit and method thereof

Abstract: The configurations and adjusting method of a successive approximation analog-to-digital converter (SAR ADC) are provided. The provided SAR ADC includes at least one capacitor with a first and a second terminals, and a plurality of bits, each of which is connected to the at least one capacitor, wherein the first terminal receives an input signal, and the second terminal selectively receives one of a first and a second reference voltages, and a first comparator receiving an adjustable third reference voltage and a first voltage value generated by the input signal, wherein a connection of the second terminal of each the capacitor of the capacitor array is switched when the first voltage value is larger than the third reference voltage.

A Multibit Dual-Feedback CT $\Delta\Sigma$ Modulator With Lowpass Signal Transfer Function

Abstract: This paper presents a dual-feedback continuous-time delta-sigma modulator that features a signal transfer function with low sensitivity to coefficient variations. The anti-aliasing of this topology is similar to that of the feedback architecture while using only two feedback paths for modulators of any order. The proposed architecture is a good candidate for low-power applications as it shows relaxed amplifier gain-bandwidth requirements for the first integrator. As a proof of concept, a third-order delta-sigma modulator has been implemented and tested which achieves 76 dB dynamic range over 5 MHz signal bandwidth while consuming 6 mW from a 1.2 V supply. The prototype chip, fabricated in a 130 nm CMOS process, provides 70 dB anti-aliasing with no out-of-band peaking in the signal transfer function.

Terabit transmission rate coherent light orthogonal frequency division multiplexing (OFDM) system based on optical comb

Abstract: The invention provides a feasible Terabit transmission rate coherent light orthogonal frequency division multiplexing system which is of simpler system structure, and comprises a transmitting end and a receiving end, wherein, the transmitting end comprises a transmitting end optical carrier generation module which comprises a transmitting end laser, an optical comb generator and an optical demultiplexer. In the system, on the basis of single light source, the optical comb generator is utilized to obtain light frequency combs with multiple wavelengths, which are used as optical carriers of base band OFDM signals, and mutually orthogonal OFDM frequency bands are generated on an optical domain, thus a plurality of radio frequency (RF) oscillation sources with complex structures are not need in the prior art. By utilizing the system, an OBM-COOFDM (orthogonal-band-multiplexed-coherent optical orthogonal frequency division multiplexing) optical signal is obtained under the condition of not using the RF oscillation sources, thus greatly reducing the complexity and cost of a transmitter; and the system has better feasibility of the OBM-COOFDM hardware, thus reducing the higher sampling rate requirements of the traditional COOFDM Terabit transceiver on a digital to analog converter (DAC) and an analog to digital converter (ADC).

Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof

Abstract: A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits.