Showing papers on "AND gate published in 1990"

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency

Abstract: The relationship between the functionality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block is examined. The investigation is done experimentally by implementing a set of industrial circuits as FPGAs using CAD (computer-aided design) tools for technology mapping, placement, and routing. A range of programming technologies (the method of FPGA customization) is explored using a simple model of the interconnection and logic block area. The experiments are based on logic blocks that use lookup tables for implementing combinational logic. Results indicate that the best number of inputs to use (a measure of the block's functionality) is between three and four, and that a D flip-flop should be included in the logic block. The results are largely independent of the programming technology. More generally, it was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block. >

Low-energy ultrafast fiber soliton logic gates.

Abstract: We have reduced the switching energy for an all-optical soliton dragging nor gate to 5.8 pJ by using a two-fiber configuration and optimizing the fiber and laser parameters. The cascadable nor gate has a fanout of six, restores both the logic level and timing, and can operate at bit rates of up to 0.2 THz. In addition, we show that soliton dragging can be represented as a generalized exclusive-or module with high functionality. Two such modules can be interconnected as nor and and gates or broadcast and routing switches.

Active matrix liquid crystal display device having improved electrostatic discharge protection

Abstract: In an active matrix liquid crystal display device an internal short circuiting bus is formed across source and gate buses outside of a display region where thin film transistors and pixel electrodes are respectively arranged in a matrix form and inside of arrays of source and gate bus terminals. At intersections of the internal short circuiting bus with the source bus and the gate bus coupling elements of a high resistance material are provided for connecting the internal short circuiting bus to the source bus and the gate bus, respectively.

Simulation of mixed switched-capacitor/digital networks with signal-driven switches

Abstract: The simulation of mixed switched-capacitor/digital (SC/D) networks containing capacitors, independent and linear-dependent voltage sources, switches controlled either by periodic or nonperiodic Boolean signals, latched comparators, and logic gates is considered. A unified linear switched-capacitor network (SCN) and mixed SC/D network simulator, SWITCAP2, and its applications to several widely used and novel nonlinear SCNs are discussed. The switches may be controlled by periodic waveforms and by nonperiodic waveforms from the outputs of comparators and logic gates. The signal-dependent modification of network topology through the comparators, logic gates, and signal-driven switches makes the modeling of various nonlinear switched-capacitor circuits possible. Simulation results for a pulse-code modulation (PCM) voice encoder, a sigma-delta modulator, a neural network, and a phase-locked loop (PLL) are presented to demonstrate the flexibility of the approach. >

Simulation techniques for mixed analog/digital circuits

Abstract: The techniques used in the iSPLICE3 simulator for the analysis of mixed analog/digital circuits are described. iSPLICE3 combines circuit, switch-level timing, and logic simulation modes and uses event driven selective-trace techniques. It also uses a hierarchical schematic capture package called iSPI (Simulation Program Interface) for design entry, circuit partitioning, and simulation control. The contributions here include a new DC solution method, a mixed-mode interface modeling technique, and an automatic partitioning approach for MOS logic circuits. The details of these three methods are provided, along with the architecture and transient simulation algorithms used in iSPLICE3. The results of circuit simulations and mixed-mode simulations of a CMOS static RAM, two A/D converters, and a phase-locked loop are presented. These results indicate that iSPLICE3 is between one and two orders of magnitude faster than SPICE2 with negligible loss in accuracy. >

Dual mode combining circuitry

Abstract: A video signal processor includes cicuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit adders, each of which has a carry-in input terminal and a carry-out output terminal. The carry-out output terminal of one of the adders is selectively coupled, via an AND gate, to the carry-in input terminal of the other adder. The AND gate is controlled by the mode control signal. In the mode where the circuitry operates as two eight-bit adders, additional circuiry is included to detect output values which may exceed the zero to 255 range of valid values and to saturate these invalid values either at zero or 255.

Method for forming a MOSFET with substrate source contact

Abstract: A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N + , N-,P-, N + regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N + interface. A buried P-, N + short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N + substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.

Semiconductor device with insulated gate transistor

Abstract: An insulated gate transistor comprises source regions; drain regions; channel regions provided between the source and drain regions; a gate electrode; and gate insulative film provided between the channel regions and the gate electrode. The device has a semiconductor region which is provided so as to be in contact with the channel regions and has the same conductivity type as that of the channel region and has an impurity concentration higher than that of the channel region. The gate electrode has at least two opposite portions which face each other.

Choice of power-supply voltage for half-micrometer and lower submicrometer CMOS devices

Abstract: The tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometer gate lengths, taking into account high-field effects on MOSFETs. Some guidelines for optimum power-supply voltage and process/device parameters for half-micrometer and lower submicrometer CMOS devices are proposed in order to maintain MOS device reliability and achieve high circuit performance. It is shown that power-supply voltage must be reduced to maintain reliability and improved performance and that the optimum voltage reduction follows the square root of the design rule. Trends for scaling down power-supply voltage have been experimentally verified by results obtained from measurements on CMOS devices over a wide range of gate oxide thickness (7-45 nm) and gate lengths (0.3-2.0 mu m). >

Semiconductor memory device having flip-flop circuits

Abstract: A semiconductor static random access memory having a high α-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

Optoelectronic relay circuit having charging path formed by a switching transistor and a rectifying diode

Abstract: A semiconductor relay circuit includes an output FET connected to a diode array. The diode array generates a photovoltaic output in response to a light signal from a light emitting element. Across the drain and gate of the FET is a series circuit of a semiconductor device and a rectifier is connected, the switching transistor is being made conductive upon receipt at the diode array of the light signal and forms a charge current path for an accumulated charge across the gate and source of the FET. The rectifier restrains a photocurrent from reversely flowing between the drain and gate of the FET. Turning-on and turning-off operations of the relay circuit can be thereby made both achievable at a higher speed, and the reverse flow of the photocurrent upon the conduction of the output FET can be prevented from occurring.

An efficient and flexible architecture for high-density gate arrays

Abstract: The properties and performance of high-density gate arrays (HDGAs) are largely determined by the structure on which logic and memory functions are mapped. An architecture for an effective implementation of these functions is presented. All architecture in which each basic cell provides three nMOS and three pMOS transistors is given. Both nMOS and pMOS transistors share a common gate. The advantages of such an architecture can be fully exploited in memory and logic array structures like ROM, RAM, and PLA. Triple-metal BiCMOS processes are at present used to implement HDGAs. Replacing the expensive third metal layer with a TiSi/sub 2/ layer increases the silicon cost and processing time by no more than 5%. These straps are used to bridge only short distances, such as those within logic cells. They are also used for connecting transistors in parallel for increased driving capability. To show the benefits of the common-gate architecture, a 10*10-b fully pipelined multiplier was designed in custom standard cells using commercially available place-and-route software and then in an HDGA architecture. >

Method and apparatus for testing LCD panel array using a magnetic field sensor

Abstract: An LCD panel or the like is tested by determining whether any short circuit defects are present. The panel is tested for short circuit defects by scanning gate lines and drive lines with a magnetic field pickup device while a current is applied to a shorting bar which shorts together a plurality of gate lines or a plurality of drive lines. When a short circuit defect is present, a current flows through the shorted area. As a result, a corresponding magnetic field is generated along the involved lines. For a cross-short defect, the location of the defect is identified as the intersection of the drive line and gate line which generate magnetic fields of substantially the same strength.

Irredundant sequential machines via optimal logic synthesis

Abstract: It is shown that optimal sequential logic synthesis can produce irredundant, fully testable finite-state machines. Synthesizing a sequential circuit from a state-transition-graph description involves the steps of state minimization, state assignment, and logic optimization. It is also shown that 100% testability can be ensured without the addition of extra logic and without constraints on the state assignment and logic optimization. There is no area/performance penalty associated with this approach. This technique can be used in conjunction with previous approaches to ensure that the synthesized machine is easily testable. Given a state-transition-graph specification, a logic-level automation that is fully testable for all single stuck-at faults in the combinational logic without access to the memory elements can be synthesized. These procedures represent an alternative to a scan-design methodology, without the latter's usual area and performance penalty. >

Active matrix liquid crystal display element

Abstract: In an active matrix liquid crystal display element an internal short circuiting bus (32) is formed across source and gate buses (18,19) outside of a display region where thin film transistors (16) and pixel electrodes (15) are respectively arranged in a matrix form and inside of arrays of source and gate bus terminals. At intersections of the internal short circuiting bus (32) with the source bus (18) and the gate bus (19) coupling elements of a high resistance material are provided for connecting the internal short circuiting bus to the source bus and the gate bus, respectively.

Actuated gate valve with manual override

Abstract: An improved gate valve having a body with a gate positioned therein to reciprocate between positions opening and closing flow through the body, a pressure responsive actuator connected to move the gate stem, a manual override stem and an overriding drive connection connecting both the actuator and the manual override stem to the gate stem so that the gate stem and gate are moved by both the actuator and by the manual override stem independently of the actuator. A modified form of the invention is provided for directly connecting to an extension of an actuator stem for operating a valve manually. In another modified form, camming element and a camming extension are provided to increase the forces providing release of the paddles from within a groove on the interior of the housing so that the locking action of the paddles do not prevent proper operation of the mechanism.

Method of logic gate reduction in a logic gate array

Abstract: A method of gate reduction in a gate width limited logic array Common sub-groups of inputs associated with an array output are collected Logical functions are then reimplemented, using the common subgroups implemented as single gates resulting in an implementation of the logical functions that uses few active devices The method uses a constraint typically placed on gate array logic that gates wider than four inputs cannot be used The method is applicable to combinatorial digital logic devices only The method of the present invention is applicable to large scale integration (LSI) and very large scale integration (VLSI) integrated circuit devices

Precision tristate output driver circuit having a voltage clamping feature

Abstract: A tristate output driver circuit (30, 40, 50) includes first (Q7) and second (Q8) switches for selectively connecting a logic high voltage source (VH) or a logic low voltage source (VL) to an output terminal (12) in a first, connected mode. Control nodes (14, 16) on the first and second switches (Q7, Q8) are energized in a precise, symmetrical manner to prevent multiple slopes in the output waveform by a precision input stage (31) that includes cascode outputs (Q17, Q18), cascode current sources (Q19-Q20, Q21-Q22) and bootstrapped current sources (32, 34). In a second, tristate mode, the output terminal (12) is electrically isolated from the logic high (VH) and logic low voltage sources (VL). In the tristate mode, the off-switch remains off and the on-switch is turned off by the precision input stage (31) to minimize glitches in the output waveform. A voltage clamping circuit (41, 43) clamps the control nodes (14, 16) of the switches (Q7, Q8) to a voltage more negative than a termination voltage source (Vterm), the logic low voltage source (VL), or the logic high voltage source (VH) in order that the electrical isolation of the tristate mode is maintained regardless of the value of the termination voltage (Vterm).

Light-emitting memory element array and light-receiving and light-emitting module using same

Abstract: PURPOSE: To enable miniaturization, the decrease of the number of external extraction wirings and the simplification, etc., of assembly, and to integrate parts easily by using a switching element array capable of selectively transferring an ON state to other switching elements successively and a light-emitting element array. CONSTITUTION: A switching element T 31 is brought to an ON state by starting pulses, and gate potential reaches approximately zero V. On the other hand, potential 5V by a power supply VGK is applied by a resistor RL regarding the gate potential G 21 of a switching element T 21 through a diode D 21 . Gate potential G 41 through a diode D 31 reaches approximately 1V. Consequently, the gate voltage of light-emitting memory elements S 21 , S 31 and S 41 is also set at voltage 5V, 0V and 2V corresponding to the voltage of the gates G 21 , G 31 and G 41 of the elements T 21 , T 31 and T 41 . As a result, when DC potential of Ch2-Ch4 is set previously between 1V-2V, only the element S 31 corresponding to the turned-ON element T 31 in a switching element array SR1 is light-emitted. Accordingly, a plurality of transmitted optical signals can be selected independently by a plurality of the addresses sides, thus allowing high reliability at low cost. COPYRIGHT: (C)1992,JPO&Japio

The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in BF 2 implanted P+ gate p-channel MOSFETs

Abstract: A study of the effects of P+ poly gate microstructure and gate oxide cycle on boron penetration from gate electrode through thin oxide is reported. The boron diffusion and the trap generation in the oxide can be significantly reduced by using an as-deposited amorphous Si gate and an oxide cycle which incorporates less Cl into the film. A strong interaction between fluorine and boron results in boron penetration into the channel and electron trap generation in the oxide. A larger grain size means fewer grain boundaries are available for boron and fluorine diffusion from the P+ gate to oxide. Less fluorine in the oxide results in less electron trap generation and less boron penetration to the Si substrate. A smaller content of Cl in the oxide results in a reduction of boron penetration. Finally, a co-implant of boron and fluorine into the as-deposited amorphous Si gate results in minimum boron diffusion into the Si substrate, which may provide the control of fluorine dose needed to reduce the interface trap density between oxide/Si interface. Increasing the grain size of the poly gate as reported above can be applied to reduce the large concentration of fluorine introduced into the gate oxide by other processes such as CVD tungsten polycide technology

Method for manufacturing an FET with asymmetrical gate region

Abstract: A method for manufacturing a field effect transistor having source and drain regions asymmetrically arranged relative to the gate region. A strip-shaped auxiliary layer is applied in the region of the gate. A first and second spacer are laterally fashioned along an auxillary layer, the first spacer is covered with a resist mask and the second spacer is subsequently etched away. The source metallization and the drain metallization are then applied, and a planarizing passivation layer is applied therebetween. This is followed by the application of connecting metallizations for the source, drain and gate regions.

High aspect ratio asymmetric gate structures employed in novel self‐aligned high electron mobility transistor technology

Abstract: We report on the development and fabrication of high aspect ratio asymmetric gate structures defined by electron beam lithography The asymmetric gate or ‘‘gamma’’ gate, as it is referred to, has substantially lower resistance compared to gates fabricated by more conventional techniques The improved gate resistance is achieved by having an increased cross section (∼3×) over conventional T‐shaped gates, which is provided by the asymmetric fabrication scheme Concurrently, the gamma gate has been incorporated into a self‐aligned high electron mobility transistor process, in which its asymmetric shape can be used to define the gate to source and gate to drain spacings independently The unique tailoring capabilities of this fabrication technique, enables specific gate to source (Lgs), gate to drain (Lgd), and source to drain (Lsd) dimensions independent of the gate length (Lg) Devices fabricated using this technique, had an Lg of 010 μm, an Lgs of 020 μm, and an Lgd of 090 μm The total Lsd self‐aligned

Process for manufacturing integrated circuits

Abstract: The invention concerns a process for manufacturing MOS type integrated circuits comprising floating gate memory transistors, high voltage transistors and logic transistors. A first layer of oxide for the gate (3) is produced. A first layer of polycrystalline silicon (4) and an insulating layer (5) are deposited. The insulating layer (5), the first layer of polycrystalline silicon (4) and the gate oxide layer (3) are etched at the position where the logic transistors are to be installed. A second gate oxide layer (16) is produced and a second layer of polycrystalline silicon (17) is deposited. The thickness of the gate oxide layer (16) of the logic transistors is less than that of the memory transistors and the high voltage transistors, the logic transistors supporting a voltage of 3.3 V, lower than the standard voltage of 5 V.

Digital phase-lock loop system with analog voltage controlled oscillator

Abstract: A phase-lock loop scheme which can be implemented in an application specific integrated circuit using CMOS elements is disclosed which is directed to controlling a plurality of slave gate array circuits such that each of the master gate array circuit and the slave gate array circuits are clocked at the same time and are within a fixed time delay from a device reference clock signal. The master gate array circuit receives the input clock synchronization signal from the master clock of the device containing the master and gate array circuits and produces an internal clock signal which is then sent to each of the slave gate array circuits, by means of equal delay paths. The phase-lock loop circuitry utilized by each of the gate arrays can be implemented on program logic array chips along with the logic which receives the synchronized clock signals generated by the respective phase-lock loops of each of the gate array chips. Both fixed and automatic gain and damping controls for the phase-lock loops are also disclosed.

An 18 b 10 mu s self-calibrating ADC

Abstract: A self-calibrating, 18-b, serial-output, 100-ksample/s analog-to-digital converter (ADC) which is implemented on a 24-V BiCMOS analog chip and a 5-V, 2- mu m CMOS digital chip is described This partitioning allows a larger input signal for better dynamic range, eases the comparator design, and protects analog circuitry from digital feedthrough The two chips are wired in a 76-mm-wide, 16-pin plastic dual inline package (DIP) Thirteen inter-chip bonds make up the control and data interface The only other common connections to the logic supply and its ground return are made through separate wires for each chip The analog chip is a charge-balancing converter consisting of an 18-b calibrated digital-to-analog converter (DAC), an auto-zeroed latching comparator, buffers for all analog inputs, and logic for the self-timed interface to the digital chip The digital chip is a custom microcontroller which implements the calibration aid conversion algorithms, as well as the digital part of the user interface The data path on this chip includes calibration pattern generators, a successive approximation register (SAR), elements for calculating the error terms, and RAM for storing those terms >

Method of and apparatus for assigning logic gates to a plurality of hardware components

Abstract: The logic gates are usually logically arranged in a first hierarchical structure in terms of a cluster of logical functions certain logic function elements are selected as to-be-processed function elements on the basis of the number of hardware components and a maximum allowable number of gates each hardware component can accommodate. Selected to-be-processed function elements in the first hierarchical structure are classified into at least two element groups based on connection strengths among the to-be-processed function elements and a maximum allowable number of pins and gates each hardware component can carry and accommodate, respectively. Using the classification result, the selected to-be-processed function elements in the first hierarchical structure are rearranged into a second hierarchical structure in terms of a cluster of logical functions in which all of the to-be-processed function elements are partitioned into the plurality of group elements so that each of the group elements corresponds to those of the logic function elements which are physically assignable to a different one of the hardware components.

Gate latch cam

Abstract: A gate latch, using neither gravity nor springs, is forceably opened and closed from either side of the gate by a handled lever that passes between the gate and gate post an into an arcuate cam slot. When the lever is lifted, it forces open the latch to eject a gate pin and, when lowered, forces the latch to close on the gate pin.

BiCMOS gate performance optimization using a unified delay model

Abstract: A unified delay model is presented that predicts BiCMOS gate delay for both long- and short-channel MOSFETs, in low-level and high-level injection in the bipolar junction transistors (BJTs), for 5 V and reduced supply and over a wide range of circuit parameter variation. The model is applied to devise circuit and device design strategies to optimize gate performance at 5 V and at scaled supply voltage. The model predicts analytical expressions for an optimum BJT emitter length versus MOS gate width for which the delay is a minimum. To minimize performance degradation at reduced supply, an effective circuit strategy is to design with wide MOS devices and small-length BJTs. The crucial BJT parameters are (reduced) junction capacitance, (reduced) transit time and the gain-knee current product. For the MOSFET the saturation current must be maximized and gate length scaling is desirable as long as the saturation current increases

Process for the manufacture of power-mos semiconductor devices

Abstract: A process for the manufacture of power-MOS semiconductor devices achieves high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall.