Showing papers on "Barrier layer published in 2004"

Clues to the Giant Dielectric Constant of CaCu3Ti4O12 in the Defect Structure of “SrCu3Ti4O12”

Abstract: The high dielectric constant in “SrCu3Ti4O12” and the giant dielectric constant in CaCu3Ti4O12 are based on a barrier layer mechanism. Conductivity in the conducting regions is related to Ti on Cu sites. The insulating barriers are between crystallites in “SrCu3Ti4O12” but within the crystallites in CaCu3Ti4O12.

Novel high capacitance materials:- BaTiO3:La and CaCu3Ti4O12

Abstract: A review is given of the origins of high permittivity in two groups of materials, La-doped BaTiO3 and a new barrier layer capacitor material, CaCu3Ti4O12. Factors that influence permittivity include: dopant, doping mechanism, processing conditions and grain size. La-doped BaTiO3 has high permittivity due to its ferroelectric nature at low temperatures and a novel doping mechanism: A-site substitution linked to the creation of B-site vacancies for charge compensation. Permittivities of 25,000 have been achieved, which can be increased further to ∼36,000 by additional doping with Zr. The value of impedance spectroscopy to characterize materials that have heterogeneous electrical microstructures is illustrated with the example of CaCu3Ti4O12; the high permittivity is not a bulk effect, as widely stated in the literature, but is a thin layer effect typical of a barrier layer capacitor. By attention to processing conditions to achieve large grain sizes, effective permittivities as high as 300,000 have been obtained.

Atomic layer deposition of barrier materials

Abstract: Methods for processing substrate to deposit barrier layers of one or more material layers by atomic layer deposition are provided. In one aspect, a method is provided for processing a substrate including depositing a metal nitride barrier layer on at least a portion of a substrate surface by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a nitrogen containing compound and depositing a metal barrier layer on at least a portion of the metal nitride barrier layer by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a reductant. A soak process may be performed on the substrate surface before deposition of the metal nitride barrier layer and/or metal barrier layer.

Perpendicular magnetization magnetic element utilizing spin transfer

Abstract: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The method and system include providing a first pinned layer, a barrier layer, a free layer, a conductive nonmagnetic spacer layer, and a second pinned layer. Each pinned layer has a pinned layer easy axis. At least a portion of the pinned layer easy axis is in a perpendicular direction. The barrier layer resides between the first pinned layer and the free layer. The spacer layer is between the free layer and the second pinned layer. The free layer has a free layer easy axis, at least a portion of which is in the perpendicular direction. The magnetic element is also configured to allow the free layer to be switched due to spin transfer effect when a write current is passed through the magnetic element. Because of the perpendicular magnetization(s), the writing current for spin transfer may be significantly reduced.

Method and structure to improve reliability of copper interconnects

Abstract: A method of forming a conductor structure on a surface of a wafer is provided. The surface of the wafer includes cavities separated by field regions. Initially, a barrier layer is deposited on the surface that includes cavities separated by field regions. A thin seed layer with a substantially uniform thickness is deposited on the barrier layer. The barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity. The remaining volume of each cavity is filled with a conductive material which is formed on the seed layer. The conductive layer has a substantially small thickness. After forming the conductive layer, the wafer is annealed to increase grain size in the conductive layer and the seed layer.

Diffusion Studies of Copper on Ruthenium Thin Film A Plateable Copper Diffusion Barrier

Abstract: Diffusion studies were carried out on physical vapor deposited Cu/Ru(∼20 nm)/Si samples using secondary ion mass spectroscopy (SIMS) and transmission electron microscopy (TEM). Back side SIMS depth profiling revealed well-defined interfaces and showed that Cu interdiffusion was impeded by Ru thin film up to 450°C vacuum annealing. TEM showed a 20-22 nm Ru barrier layer with a columnar microstructure oriented vertically with respect to Si substrate. TEM results corroborate with SIMS data to indicate stability of the Ru film barrier for annealing temperatures up to 450°C. Direct Cu electroplating on ultrathin Ru barrier layers (<20 nm) was investigated in sulfuric acid. The electroplated Cu film is shiny, smooth, and without agglomeration under scanning electron microscopy. Excellent adhesion between interfacial layers was confirmed by the scribe-peel test. The interfacial characterization results indicate that Ru thin film is a promising candidate as a directly plateable Cu diffusion barrier.

Method of improving interlayer adhesion

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer (112) on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer (110) adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

Magnetic elements with spin engineered insertion layers and MRAM devices using the magnetic elements

Abstract: A method and system include providing a pinned layer, a free layer, and a spacer layer between the pinned and free layers. The spacer layer is nonmagnetic. The magnetic element is configured to allow the free layer to be switched due to spin transfer when a write current is passed through the magnetic element. In one aspect, the method and system include providing a spin engineered layer adjacent to the free layer. The spin engineered layer is configured to more strongly scatter majority electrons than minority electrons. In another aspect, at least one of the pinned, free, and spacer layers is a spin engineered layer having an internal spin engineered layer configured to more strongly scatter majority electrons than minority electrons. In this aspect, the magnetic element may include another pinned layer and a barrier layer between the free and pinned layers.

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Abstract: An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.

Method and apparatus for generating a precursor for a semiconductor processing system

Abstract: Embodiments of the present invention are directed to an apparatus for generating a precursor for a semiconductor processing system (320). The apparatus includes a canister (300) having a sidewall (402), a top portion and a bottom portion. The canister (300) defines an interior volume (438) having an upper region (418) and a lower region (434). In one embodiment, the apparatus further includes a heater (430) partially surrounding the canister (300). The heater (430) creates a temperature gradient between the upper region (418) and the lower region (434). Also claimed is a method of forming a barrier layer from purified pentakis (dimethylamido) tantalum, for example a tantalum nitride barrier layer by atomic layer deposition.

Copper damascene barrier and capping layer

Abstract: A method for forming a damascene with improved electrical properties and resulting structure thereof including providing at least one dielectric insulating layer overlying a first etch stop layer; forming an anti-reflectance coating (ARC) layer prior to a photolithographic patterning process; forming at least one opening extending through a thickness portion of the at least one dielectric insulating layer and first etch stop layer according to said photolithographic patterning and an etching process; blanket depositing a barrier layer including material selected from the group consisting of silicon carbide and silicon oxycarbide to line the at least one opening; blanket depositing a refractory metal liner over the barrier layer; blanket depositing at least one metal layer to fill the at least one opening; and, removing at least the at least one metal layer overlying the at least one opening level according to a chemical mechanical polish (CMP) process.

Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof

Abstract: Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.

Ruthenium as an underlayer for tungsten film deposition

Abstract: In one embodiment, a method for depositing a tungsten-containing film on a substrate is provided which includes depositing a barrier layer on the substrate, such as a titanium or tantalum containing barrier layer and depositing a ruthenium layer on the barrier layer. The method further includes depositing a tungsten nucleation layer on the ruthenium layer and depositing a tungsten bulk layer on the tungsten nucleation layer. The barrier layer, the ruthenium layer, the tungsten nucleation layer and the tungsten bulk layer are independently deposited by an ALD process, a CVD process or a PVD process, preferably by an ALD process. In some examples, the substrate is exposed to a soak process prior to depositing a subsequent layer, such as between the deposition of the barrier layer and the ruthenium layer, the ruthenium layer and the tungsten nucleation layer or the tungsten nucleation layer and the tungsten bulk layer.

Tunneling magnetoresistance in (Ga,Mn)As-based heterostructures with a GaAs barrier

Abstract: We have investigated the properties of tunneling magnetoresistance (TMR) of (Ga,Mn)As trilayer structures with a GaAs intermediary barrier layer. TMR ratio of 290% is observed at 0.39 K around zero applied bias voltage. The bias dependence of TMR ratio as well as the temperature-dependent anisotropic behavior are presented.

Sound insulating system

Abstract: The present invention relates to a sound insulating system (10). The sound insulating system (10) comprises a first sound absorbing layer (12). A barrier layer (14) is positioned adjacent the first sound absorbing layer (12). A second absorbing layer (16) is also provided and is adjacent the barrier layer (14).

Multilayer metal gate electrode

Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.

Bi-layer approach for a hermetic low dielectric constant layer for barrier applications

Abstract: Methods and apparatus are provided for processing a substrate with a bilayer barrier layer. In one aspect, the invention provides a method for processing a substrate including depositing a nitrogen containing barrier layer on a substrate surface and then depositing a nitrogen free barrier layer thereon. The barrier layer may be deposited over dielectric materials, conductive materials, or both. The bilayer barrier layer may also be used as an etch stop, an anti-reflective coating, or a passivation layer.

Self-pinned double tunnel junction head

Abstract: A thin dual magnetic tunnel junction head having a free layer and first and second antiparallel (AP) pinned layer structures positioned on opposite sides of the free layer, each of the AP pinned layer structures including at least two pinned layers having magnetic moments that are self-pinned antiparallel to each other, the pinned layers of each AP pinned layer structure being separated by an AP coupling layer. A first barrier layer is positioned between the first AP pinned layer structure and the free layer. A second barrier layer is positioned between the second AP pinned layer structure and the free layer. The head does not have any antiferromagnetic layers, and so is much thinner than dual magnetic tunnel junction sensors heretofore known. As such, dual magnetic tunnel junction heads can be fabricated at a thickness of less than about 500 Å.

Packaging for primary and secondary batteries

Abstract: A housing for a battery comprising a laminate made of a plurality of layers is provided. The battery housing has at least a barrier layer, typically two metal foils, and a sealing layer, which is intended to be in contact with the contents of a battery. Additionally, the battery housing can further include a protective layer over the barrier layer. Suitable materials for the sealant layer and barrier layers include polymers. Preferably, the laminate battery housing is flexible, although this is not required. The sealant layer, barrier layer and protective layer may also be adhesively attached. The battery housing of the present invention can also provide moisture and acid absorbers in various configurations.

Depletion-less photodiode with suppressed dark current and method for producing the same

Abstract: The invention relates to a photo-detector with a reduced G-R noise, which comprises a sequence of a p-type contact layer, a middle barrier layer and an n-type photon absorbing layer, wherein the middle barrier layer has an energy bandgap significantly greater than that of the photon absorbing layer, and there is no layer with a narrower energy bandgap than that in the photon-absorbing layer.

Cyclical deposition of tungsten nitride for metal oxide gate electrode

Abstract: A method for depositing a tungsten nitride layer is provided. The method includes a cyclical process of alternately adsorbing a tungsten-containing compound and a nitrogen-containing compound on a substrate. The barrier layer has a reduced resistivity, lower concentration of fluorine, and can be deposited at any desired thickness, such as less than 100 angstroms, to minimize the amount of barrier layer material.

Manufacturing method for large-scale production of thin-film solar cells

Abstract: A method of manufacturing improved thin-film solar cells entirely by sputtering includes a high efficiency back contact/reflecting multi-layer containing at least one barrier layer consisting of a transition metal nitride. A copper indium gallium diselenide (Cu(InxGa1-x)Se2) absorber layer (X ranging from 1 to approximately 0.7) is co-sputtered from specially prepared electrically conductive targets using dual cylindrical rotary magnetron technology. The band gap of the absorber layer can be graded by varying the gallium content, and by replacing the gallium partially or totally with aluminum. Alternately the absorber layer is reactively sputtered from metal alloy targets in the presence of hydrogen selenide gas. RF sputtering is used to deposit a non-cadmium containing window layer of ZnS. The top transparent electrode is reactively sputtered aluminum doped ZnO. A unique modular vacuum roll-to-roll sputtering machine is described. The machine is adapted to incorporate dual cylindrical rotary magnetron technology to manufacture the improved solar cell material in a single pass.

Cmos imager with cu wiring and method of eliminating high reflectivity interfaces therefrom

Abstract: An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

Sputter deposition and etching of metallization seed layer for overhang and sidewall improvement

Abstract: An integrated sputtering method and reactor for copper or aluminum seed layers in which a plasma sputter reactor initially deposits a thin conformal layer onto a substrate including a high-aspect ratio hole subject to the formation of overhangs After the seed deposition, the same sputter reactor is used to sputter etch the substrate with energetic light ions, especially helium, having an energy sufficiently low that it selectively etches the metallization to the heavier underlying barrier layer, for example, copper over tantalum or aluminum over titanium An RF inductive coil generates the plasma during the sputtering etching while the target power is turned off A final copper flash step deposits copper over the bare barrier field region before copper is electrochemically plated to fill the hole The invention also includes a simultaneous sputter deposition and sputter etch, and an energetic ion processing of the copper seed sidewall

Chromate Conversion Coating on Aluminum Alloys I. Formation Mechanism

Abstract: The formation of chromate conversion coatings (CCCs) on commercially pure Al (AA1050) during immersion in a chromic/ hydrofluoric acid solution has been investigated. A film formation mechanism is proposed based on the combination of open circuit potential measurements and surface analysis techniques, such as Auger electron spectroscopy and atomic force microscopy. It is suggested that the conversion of the Al surface takes place in three distinct stages: activation of the surface, initiation of the film formation, and growth of the conversion layer. In addition to the classical approach, a sol-gel model was considered for the initiation and growth of the film. The effect of the free fluoride and chromic acid concentration was studied using a thermodynamic model whereas the influence of the Al oxide film was investigated by forming an anodic barrier layer prior to the conversion process. It was shown that the rate-determining step in the CCC formation is the activation of the Al surface. Therefore, the morphology and structure of the conversion layer is determined not only by the bath composition but also by the thickness of the Al oxide film.

Dual damascene diffusion barrier/liner process with selective via-to-trench-bottom recess

Abstract: A method for fabricating a barrier layer. A first barrier layer (124) is deposited over a dielectric (104) including in a trench (108) and via (106). A re-sputtering process is then performed to remove said first barrier layer (124) from a bottom of the via (106) without substantially reducing a thickness of said first barrier layer (124) at a bottom of the trench (108) using an intermediate DC target power. A second barrier layer (126) is then deposited.

Barrier in gate stack for improved gate dielectric integrity

Abstract: A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.

GaN/AlGaN/GaN DISPERSION-FREE HIGH ELECTRON MOBILITY TRANSISTORS

Abstract: A dispersion-free high electron mobility transistor (HEMT), comprised of a substrate; a semi-insulating buffer layer, comprised of gallium nitride (GaN) or aluminum gallium nitride (A1GaN), deposited on the substrate, an A1GaN barrier layer, with an aluminum (Al) mole fraction larger than that of the semi-insulating buffer layer, deposited on the semi-insulating buffer layer, an n-type doped graded A1GaN layer deposited on the A1GaN barrier layer, wherein an Al mole fraction is decreased from a bottom of the n-type doped graded A1GaN layer to a top of the n-type doped graded A1GaN layer, and a cap layer, comprised of GaN or A1GaN with an Al mole fraction smaller than that of the A1GaN barrier layer, deposited on the n-type doped graded A1GaN layer.

Dielectric barrier layer films

Abstract: In accordance with the present invention, a dielectric barrier layer is presented. A barrier layer according to the present invention includes a densified amorphous dielectric layer deposited on a substrate by pulsed-DC, substrate biased physical vapor deposition, wherein the densified amorphous dielectric layer is a barrier layer. A method of forming a barrier layer according to the present inventions includes providing a substrate and depositing a highly densified, amorphous, dielectric material over the substrate in a pulsed-dc, biased, wide target physical vapor deposition process. Further, the process can include performing a soft-metal breath treatment on the substrate. Such barrier layers can be utilized as electrical layers, optical layers, immunological layers, or tribological layers.