Showing papers on "Chip published in 2004"

IBM Power5 chip: a dual-core multithreaded processor

Abstract: IBM introduced Power4-based systems in 2001. The Power4 design integrates two processor cores on a single chip, a shared second-level cache, a directory for an off-chip third-level cache, and the necessary circuitry to connect it to other Power4 chips to form a system. The dual-processor chip provides natural thread-level parallelism at the chip level. The Power5 is the next-generation chip in this line. One of our key goals in designing the Power5 was to maintain both binary and structural compatibility with existing Power4 systems to ensure that binaries continue executing properly and all application optimizations carry forward to newer systems. With that base requirement, we specified increased performance and other functional enhancements of server virtualization, reliability, availability, and serviceability at both chip and system levels. We describe the approach we used to improve chip-level performance.

Chip stack package and manufacturing method thereof

Abstract: A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

Power harvesting and telemetry in CMOS for implanted devices

Abstract: Implanted sensors offer many advantages to those studying the behavior of the human body. Unfortunately, the need to power and communicate with devices often requires tradeoffs that compromise their usefulness. We describe a power harvesting and telemetry chip that allows operation without wires or batteries. The chip has been fabricated in 0.5 /spl mu/m CMOS. The chip is able to supply 2 mA at 33 V to associated sensors using inductive coupling. Tests reveal the characteristics of this chip under different loads and at different distances from the transmission coil. With the preliminary coils, functionality could be maintained with over 28 mm between the two coils. To evaluate the performance of the chip in conditions mimicking implantation in the body, water bearing colloids were introduced between the two coils. This resulted in a small loss of transfer efficiency, with no change in the behavior of the chip.

Intermediate chip module, semiconductor device, circuit board, and electronic device

Abstract: An intermediate chip for electrically connecting semiconductor chips includes: a substrate having a first side and a second side; a trans-substrate conductive plug which projects to the first side of the substrate; a post electrode which is displaced from the trans-substrate conductive plug in plan view on the second side of the substrate; and wiring which is disposed in or on the substrate for coupling the trans-substrate conductive plug and the post electrode.

Digital pulse width modulator architectures

Abstract: This paper presents a survey and classification of architectures for integrated circuit implementation of digital pulse-width modulators (DPWM) targeting digital control of high-frequency switching DC-DC power converters. Previously presented designs are identified as particular cases of the proposed classification. In order to optimize circuit resources in terms of occupied area and power consumption, a general architecture based on tapped delay lines is proposed, which includes segmentation of the input digital code to drive binary weighted delay cells and thermometer-decoded unary delay cells. Integrated circuit design of a particular example of the segmented DPWM is described. The segmented DPWM prototype chip operates at 1 MHz switching frequency and has low power consumption and very small silicon area (0.07 mm/sup 2/ in a standard 0.5 micron CMOS process). Experimental results validate the functionality of the proposed segmented DPWM.

Proximity communication

Abstract: This paper reports results from wireless chip-to-chip communication experiments. Sixteen bit words pass from one chip to another in parallel without detectable error at 1.35 billion data items per second for a total data rate of 21.6 Gigabits per second. The experiment transmits pseudo random patterns between chips built in a 350-nm CMOS technology. Chips touch face-to-face to communicate. The same pseudorandom data pattern is loaded onto both chips so that the receiving chip can check the accuracy of every bit communicated. Each communication channel consumes a static power of 3.6 mW, and a dynamic power of 3.9 pJ per bit communicated. The channels lie on 50-/spl mu/m centers. Because the capacitive communication works through covering oxide, ESD protection is unnecessary. Vernier position measuring circuits built into the chips indicate the relative position of transmitting and receiving arrays to assist mechanical alignment. The test chip includes a Vernier measurement circuit that provides inter-chip position measurements with a resolution of 1.4 /spl mu/m.

Triple multiplexing spread spectrum receiver

Abstract: A spread spectrum receiver processes signals from a plurality of sources modulated by different spread spectrum codes by sampling the signals as received to produce an integer series of sampling segments at a sampling rate at least twice a chip rate of the codes, each sampling segment containing an integer number of bits representing a fraction of a chip of the codes, time division multiplexing each sample segment into a number of channels, correlating the bits in each sample segment in each channel in parallel with a source specific series of locally generated sequential code samples differing by one bit, summing each parallel correlation, and accumulating the summed parallel correlations for each code sample in each channel at a rate at least equal to the chip rate to derive data related to each of the sources.

Evaluation of Single Phase Flow in Microchannels for High Heat Flux Chip Cooling—Thermohydraulic Performance Enhancement and Fabrication Technology

Abstract: The increased circuit density on today's computer chips is reaching the heat dissipation limits for air-cooling technology. The direct liquid cooling of chips is being considered as a viable alternative. This paper reviews liquid cooling with internal flow channels in terms of technological options and challenges. The possibilities presented herein indicate a four- to ten-fold increase in heat flux over the air-cooled systems. The roadmap for single-phase cooling technology is presented to identify research opportunities in meeting the cooling demands of future IC chips. The use of three-dimensional microchannels that incorporate either microstructures in the channel or grooves in the channel surfaces may lead to significant enhancements in single-phase cooling. A simplified and well-established fabrication process is described to fabricate both classes of three-dimensional microchannels. Proof-of-concept microchannels are presented to demonstrate the efficacy of the fabrication process in fabricating com...

A static model of chip formation in microscale milling

Abstract: This paper discusses the development of an enhanced, static model of chip formation in micromilling processes that is able to describe the intermittency of the chip formation observed at low feeds per tooth due to the dominance of the minimum chip thickness effect. Experimental analyses demonstrate the validity of the proposed model by verifying the level of periodicity in the cutting forces present at various feeds per tooth. A key finding of this study is the identification of a local maximum in the radial thrust forces in the micromilling process during the noncutting regime, at feeds per tooth that are of the order of the minimum chip thickness. To overcome the challenges in the direct measurement of the minimum chip thickness, this paper presents a method for estimating the minimum chip thickness of various combinations of tools and workpiece materials based on easily attainable cutting-force data. A discussion on the selection of process parameters to avoid intermittent chip formation is also presented.

Single chip protocol converter

Abstract: A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.

Semiconductor integrated circuit device

Abstract: A semiconductor integrated circuit device which requires high packaging density adopts a method for forming bumps in a terminal section of a semiconductor chip and bonding the semiconductor chip directly on a substrate. In this case, in order to prevent damage to the semiconductor integrated chip, which would otherwise be caused by bonding pressure employed at the time of bonding operation, non-connected dummy bumps are provided at corner sections of the semiconductor chip. Even when the dummy bumps are provided, there arises a necessity for preventing an increase in the size of the semiconductor chips, which would otherwise arise when the dummy bumps are provided on the chip.

Activating a data tag by load or orientation or user control

Abstract: Mechanically and reversibly activating or deactivating a radio frequency identification (RFID) data tag. An RFID tag includes an RFID chip for storing an RFID code, an antenna for communicating a radio frequency (RF) signal, and a mechanical switch coupling the RFID chip to the antenna. Closing the mechanical switch enables the RFID chip and the antenna to communicate the RFID code via the RF signal.

Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times

Abstract: This paper presents an intra-process dynamic voltage and frequency scaling (DVFS) technique targeted toward non real-time applications running on an embedded system platform. The key idea is to make use of runtime information about the external memory access statistics in order to perform CPU voltage and frequency scaling with the goal of minimizing the energy consumption while translucently controlling the performance penalty. The proposed DVFS technique relies on dynamically-constructed regression models that allow the CPU to calculate the expected workload and slack time for the next time slot, and thus, adjust its voltage and frequency in order to save energy while meeting soft timing constraints. This is in turn achieved by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time. The proposed technique has been implemented on an XScale-based embedded system platform and actual energy savings have been calculated by current measurements in hardware. For memory-bound programs, a CPU energy saving of more than 70% with a performance degradation of 12% was achieved. For CPU-bound programs, 15/spl sim/60% CPU energy saving was achieved at the cost of 5-20% performance penalty.

The development of scalable sensor arrays using standard CMOS technology

Abstract: This paper describes an approach to developing MOSFET-based scalable sensor arrays in an unmodified standard CMOS process. The multiplexed design can be used as either a single-ended or differential circuit to make potentiometric measurements in each cell of the array. The FET-based sensors employ a floating gate electrode structure and use the nitride passivation layer as a pH-sensitive membrane. An implementation of a single-chip 2×2 array fabricated in an unmodified commercial 0.35 μm CMOS process is presented. All signal acquisition is performed in-situ and all readout circuitry is located on-chip. On return from the foundry, the devices are exposed to ultraviolet light to eliminate any difference in threshold voltage. The circuit provides a sufficient linear range that allows the FET devices to operate as pH sensors in the array. A double layer of SU-8 photoresist is used to provide both a biocompatible and waterproof package for the chip. The biocompatibility of the chip surface is investigated using a well-established cell line.

A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process

Abstract: A discrete-time receiver architecture for a wireless application is presented. Analog signal processing concepts are used to directly sample the RF input at Nyquist rate. Maximum receiver sensitivity is -83dBm and the chip consumes a total of 41mA from a 1.575V internally regulated supply. The receiver is implemented in a 0.13/spl mu/m digital CMOS process.

A dynamically reconfigurable SIMD processor for a vision chip

Abstract: Conventional SIMD image processors are very effective for early visual processing because of their parallelism. However, in performing more advanced processing, they exhibit some problems, such as poor performance in global operations and a tradeoff between flexibility of processing and the number of pixels. This paper shows a new architecture and sample algorithms of a vision chip that has the ability to reconfigure its hardware dynamically by chaining processing elements. A prototype chip with 64/spl times/64 pixels manufactured using the 0.35-/spl mu/m CMOS process is also shown.

Radio frequency identification (RFID) tag and manufacturing method thereof

Abstract: An RFID tag includes a dielectric member, an antenna pattern formed on and around a surface of the dielectric member, and an IC chip that is electrically connected to the antenna pattern by means of two chip pads.

Multi-chips stacked package

Abstract: A multi-chips stacked package comprises a substrate, an upper chip, a lower chip, a dam, a heat spreader, an underfill, a plurality of first electrically conductive bumps and a plurality of second electrically conductive bumps. The upper chip is flip-chip bonded to the upper surface of the substrate and the second chip is accommodated in the opening and flip-chip bonded to the upper chip. Furthermore, the dam is disposed on the substrate and supports the heat spreader so as to fix the heat spreader to the back surface of the first chip. In addition, the underfill is filled into the space which is enclosed by the dam, the upper surface of the substrate and the heat spreader. In such a manner, at least the upper chip, the lower chip, the first and second electrically conductive bumps and a portion of the substrate are covered by the underfill. Thus, the underfill is connected to the dam, the heat spreader and the substrate simultaneously, so the reinforced structure including the heat spreader, the underfill and the dam can restrain the thermal deformation of the substrate and the upper chip and prevent the first electrically conductive bumps connecting the upper chip and the substrate from being damaged.

Precise temperature control in microfluidic devices using Joule heating of ionic liquids

Abstract: Microfluidic devices for spatially localised heating of microchannel environments were designed, fabricated and tested The devices are simple to implement, do not require complex manufacturing steps and enable intra-channel temperature control to within ±02 °C Ionic liquids held in co-running channels are Joule heated with an ac current The nature of the devices means that the internal temperature can be directly assessed in a facile manner

Semiconductor device and method of manufacturing the same

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which has improved manufacturing yield and efficiency through improvement of wiring structure and also realized reduction in manufacturing cost even when a plurality of semiconductor chips are laminated. SOLUTION: A plurality of chip connecting wires 8 in which a plurality of semiconductor chips 2 including a plurality of terminals 5 are electrically connected to each terminal 5 are formed substantially in the same pattern. Moreover, the semiconductor chip is mounted at least one by one on the two sheets of chip mounting base material 6 which are laminated in two layers in the thickness direction. A sheet of wiring base material 15, in which a plurality of intermediate wires 17 electrically connected to each connecting wiring 8 are formed in the pattern which is different from that of each connecting wiring 8, is allocated between each mounting base material 6. Within a plurality of through-holes which are provided through each mounting base material 6 and wiring base material 15 in the laminating direction thereof, a plurality of interlayer connecting wires 30 are formed to electrically connect each connecting wiring 8 and each intermediate wiring 17 in the laminating direction of the base materials 6, 15. COPYRIGHT: (C)2004,JPO

Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

Abstract: For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 /spl mu/m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element selection and precise measurement are achieved with low parasitic resistance measurement buses and leakage-controlled switching circuits, which allow the measurement accuracy for a transistor, resistor, or capacitor of 90 pA, 11 m/spl Omega/, and 23 aF, respectively, in the 3/spl sigma/ range. The ability to obtain 29 008 samples from a chip enables statistical analysis of the variation in 148 elements of each chip with 240-/spl mu/m spatial resolution. This high resolution and large sample number allows us to precisely decompose the data into systematic and random variation parts with newly developed fourth-order polynomial fitting. Our methodology has been verified using a test chip fabricated by a 130-nm CMOS process with a 100-nm physical gate length and five Cu interconnect layers. In MOSFETs, the random part was dominant and indicated a certain /spl sigma/ value in every chip. In the case of the interconnect layers, the random and systematic parts of the resistance and the capacitance indicated variance fluctuations. By chip, by item, by size, by structure, random or systematic, the /spl sigma/ values of each variation show inconsistency which we believe is attributable to the Cu process. The correlation coefficients of systematic part between device element and ring oscillator frequency shown very high value (0.87-0.98), and those of a random part were low enough (-0.10-0.22) to prove the accuracy of decomposition.

Stacked flip chip package

Abstract: A stacked flip-chip package comprises a substrate having an opening, a back-to-face chip module, and an encapsulant. The back-to-face chip module is attached to the substrate and encapsulated by the encapsulant. The back-to-face chip module includes a first chip and a second chip. The first chip has a first active surface and a first back surface. Redistributed traces are formed on the first back surface. The second chip is flip-chip mounted on the first back surface of the first chip and electrically connected to the redistributed traces. A plurality of bumps connect the redistributed traces to the top surface of the substrate. Thus the second chip can be accommodated inside the opening and the redistributed traces are electrically connected to the second chip and the substrate so as to achieve fine pitch flip-chip mounting and improve the electrical performance and heat dissipation efficiency for the back-to-face chip module.

A high-speed 128-kb MRAM core for future universal memory applications

Abstract: A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.

Vertical system integration by using inter-chip vias and solid-liquid interdiffusion bonding

Abstract: A new approach for 3D system integration, called Inter Chip Via-Solid Liquid Interdiffusion (ICV-SLID) is introduced. This is a new chip-to-wafer stacking technology which combines the advantages of the Inter Chip Via (ICV) process and the solid-liquid-interdiffusion technique (SLID) of copper and tin. The fully modular ICV-SLID concept allows the formation of multiple device stacks. A test chip was designed and the total process sequence of the ICV-SLID technology for the realization of a three-layer chip-to-wafer stack was demonstrated. The proposed wafer-level 3D integration concept has the potential for low cost fabrication of multi-layer high-performance 3D-SoCs and is well suited as a replacement for embedded technologies based on monolithic integration.

Chip-to-chip communication system using an ac-coupled bus and devices employed in same

Abstract: A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

Formation of circuitry with modification of feature height

Abstract: A connection component for mounting a chip or other microelectronic element is formed from a starting unit including posts projecting from a dielectric element by crushing or otherwise reducing the height of at least some of the posts.

Chip package structure and manufacturing method thereof

Abstract: The present invention provides a chip package structure and the manufacturing method thereof, which affords higher heat dissipation efficiency and is suitable to fabricate the stack type package structure with a higher integration The chip package structure comprises a carrier, at least a chip, a heat sink and a mold compound The chip is disposed on the carrier, while the bonding pads of the chip are electrically connected to the leads of the carrier The heat sink is disposed over the chip and includes at least a body and a plurality of connecting portions The connecting portions are disposed around a periphery of the body and are electrically connected to the leads By using a specially designed heat sink, the chip package structure can afford better heat dissipation and be suitable to form stack type package structures

Command controlling different operations in different chips

Abstract: In some embodiments, the invention includes a chip having a register to include an operation type signal. The chip also includes control circuitry to receive a first command and in response to the first command to cause the chip to perform a first operation if the operation type signal has a first value and to cause the chip to perform a second operation if the operation type signal has a second value. The chip may be a memory chip in a memory system. Other embodiments are described and claimed.

Method and system for expanding flash storage device capacity

Abstract: Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories. In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to one of the Flash memory chips.