Showing papers on "Clock generator published in 2017"

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI

Abstract: This paper presents a RISC-V system-on-chip (SoC) with integrated voltage regulation, adaptive clocking, and power management implemented in a 28 nm fully depleted silicon-on-insulator process. A fully integrated simultaneous-switching switched-capacitor DC–DC converter supplies an application core using a clock from a free-running adaptive clock generator, achieving high system conversion efficiency (82%–89%) and energy efficiency (41.8 double-precision GFLOPS/W) while delivering up to 231 mW of power. A second core serves as an integrated power-management unit that can measure system state and actuate changes to core voltage and frequency, allowing the implementation of a wide variety of power-management algorithms that can respond at submicrosecond timescales while adding just 2.0% area overhead. A voltage dithering program allows operation across a wide continuous voltage range (0.45 V–1 V), while an adaptive voltage-scaling algorithm reduces the energy consumption of a synthetic benchmark by 39.8% with negligible performance penalty, demonstrating practical microsecond-scale power management for mobile SoCs.

Clock Technology: The Next Frontier

Abstract: Clocking of electrical circuit is a crucial issue since clock signal is used to establish the flow-of-time inside electronic world Before, during and after the "Moore's law", flow-of-time is an eternal issue Alongside processor, memory/storage and analog/ RF technologies, IC clocking could be regarded as the 4th major IC design technology In the past several decades, clock is mostly used in the form of fixed-frequency with high frequency stability For future system, however, this type of clock signal is not sufficient because its usage environment is not expected to be stationary but dynamic To meet this challenge, innovation in IC clocking is required This paper first discusses the difficulties in creating flow-of-time; then the two long-lasting problems in clock generation are identified, and then new challenges in the design of future system are summarized Afterwards, the Time-Average-Frequency based flexible clock generator is introduced and its potential to confront these challenges is addressed Several major issues in modern design are discussed The paper concludes with a vision that, for electronic system to improve its information processing efficiency to next level, clock technology is the next frontier to be explored

29.7 A 2.5GHz injection-locked ADPLL with 197fs rms integrated jitter and −65dBc reference spur using time-division dual calibration

Abstract: A clock generator using an injection-locked oscillator (ILO) offers remarkable jitter performance with low-overhead of additional circuits such as injection switches. Because the injection clock cleans the edge of the oscillator in every injection period, jitter accumulation is avoided. However, the ILO alone causes a severe reference spur owing to the mismatch between the desired oscillation frequency set by the injected reference and the free-running frequency that could change over the process, supply voltage, and temperature (PVT) variations [1]. For this reason, continuously tuning the free-running oscillation frequency, F OSC , to nullify the frequency error, F ERR , is required. Here F ERR is the frequency difference between F OSC and the multiplication ratio, N, times the reference frequency, F REF . For minimizing such performance degradations, techniques such as pulse gating [2] and replica-delay cells [3] have been presented. While the minimization of F ERR is achieved, the path delay mismatch between the injection and the phase detector remains unsolved, limiting the spur reduction capability. Thus, a precise calibration for equalizing the delay mismatch is required for achieving low spur performance. This paper proposes an injection-locked all-digital phase-locked loop (IL-ADPLL) with a time-division dual calibration (TDDC) scheme for reducing the reference spur with robust performance against PVT variations.

On-Chip Two-Tone Synthesizer Based on a Mixing-FIR Architecture

Abstract: A low-distortion current-steering two-tone sinusoidal signal synthesizer based on a mixing-finite impulse response (FIR) architecture is proposed. The proposed robust synthesizer adopts only digital blocks. It implements a two-stage cascade FIR harmonic cancellation technique that generates a single tone quasi-sinusoidal waveform and suppress the odd-order harmonics up to the 21st order. Differential-mode circuitry and a 50% duty cycle clock are also utilized to cancel the even-order harmonics. The single-tone signal is further up-converted to the desired local oscillator (LO) frequency band, thereby producing the desired two-tone sinusoidal signals. The proposed synthesizer contains a current mirror array implementing the FIR tap coefficients. Accuracy is enhanced using dynamic element matching. The other building blocks consist of a 24-phase clock generator, a current combiner, and a passive mixer with bootstrapped MOS switches. This two-tone synthesizer can be used to conduct a linearity built-in self-test. It is fabricated in 130-nm standard CMOS technology, occupying a 0.056-mm2 silicon area. Measurement shows better than −68 dBc third-order intermodulation (IM3) below 480-MHz LO frequency without calibration. For the LO frequency <76.8 MHz and the two-tone difference <2 MHz, an IM3 better than −75 dBc can be achieved. The imbalance between the two-tone amplitudes is measured <0.1 dB across the whole frequency range from dc to 1 GHz.

A 0.1–0.6 V input range voltage boost converter with low-leakage driver for low-voltage energy harvesting

Abstract: This paper proposes a fully integrated voltage boost converter (VBC) for low-voltage energy harvesting The proposed VBC consists of three stage charge pumps (CPs) with a low-leakage driver, ring oscillator, and 4-phase clock generator The output voltage is four times higher than an input voltage Fin The low-leakage driver generates control signals to operate CPs with low leakage current The amplitude of the control signals is 2V IN and does not depend on the load current The proposed VBC achieves a wide load current, high output voltage, and high efficiency, even with a low-voltage input of the harvester Simulation results demonstrated that the proposed VBC converted 01-V input to 0362-V output and 06-V input to 238-V output, when the load current is zero The peak efficiency was 703% at a 06-V input and 1-mA load current

A 0.015-mm $^{\text{2}}$ Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology

Abstract: This brief illustrates the design of an inductorless high-speed clock generator. Compared to inductance-capacitance ( $LC$ ) oscillators, ring oscillators are used in order to achieve a wide frequency-tuning range with a small chip area. By employing a cascaded phase-locked loop (PLL) architecture, the phase noise of the oscillator can be effectively suppressed. The first PLL is implemented with high-voltage devices under 1.8-V supply to provide a clean reference for the second PLL. The second PLL consists of only low-voltage devices, with a supply voltage of 0.9 V for high-speed operation. Following the second PLL, a clock doubler multiplies the PLL output clock by a factor of 2, which avoids power-consuming high-frequency clock dividers. In order to minimize any mismatch effects, special layout techniques are employed for the second voltage-controlled oscillator and the clock doubler. The prototype chip was fabricated in 28-nm complementary metal oxide semiconductor (CMOS) technology, and it occupies an active area of only 0.015 mm2. The proposed PLL achieves a maximum output frequency of 32 GHz and consumes a total power of 30 mW, exhibiting a power efficiency of 0.9 mW/GHz.

Application of Ellipse Fitting Algorithm in Incoherent Sampling Measurements of Complex Ratio of AC Voltages

Abstract: This paper presents a comparison of results of coherent and incoherent sampling measurements of complex ratios of sinusoidal voltages, obtained with the use of an ellipse-fitting algorithm (EFA) and with the use of discrete Fourier transform (DFT). The EFA algorithm has not been yet used in the measurements of the complex voltage ratio. Known applications of EFA in impedance measurements were based on simultaneous sampling of two voltages by a two-channel aquisition card. Measurements presented in this paper were made with an automated measurement system consisting of Keysight 3458A multimeter operating in the DC voltage sampling mode. The internal 20-MHz clock generator of this multimeter was replaced with a custom-made clock module dividing the clock frequency by 2 and providing fiber optic 10–MHz synchronization signal. This signal was used as the reference frequency of the Keysight 33250A generator which served as a reference frequency clock for the dual-channel source of digitally synthesized sinusoidal voltage. Because the output frequency of the Keysight 33250A generator can be adjusted with very high resolution and accuracy, it was possible to perform coherent and incoherent sampling measurements with controlled frequency deviation.

8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment

Abstract: Digital PLLs are popular for on-chip clock generation due to their small size and technology portability. Variability tolerance is a key design challenge when designing such PLLs in an advanced CMOS technology. Environmental variations, such as mismatch, process, supply voltage, and temperature (PVT) perturb device characteristics and result in performance changes, such as DCO gain and noise. Another consideration is the wide range of operating modes in which modern digital circuits (e.g., processors) operate. For instance, a clock generator for a processor may produce a range of frequencies from tens of MHz to several GHz depending on required processor performance. In low-frequency mode, the power consumption is more pronounced than the noise. Therefore, we seek to design a PLL that is both insensitive to environmental variations, as well as reconfigurable to changing noise and power specifications.

DC-62 GHz 4-phase 25% duty cycle quadrature clock generator

Abstract: A process-, temperature-and supply-insensitive DC-to-62GHz 4-phase quadrature generator for clock signals with 25% duty cycle was manufactured in a production 55-nm SiGe BiCMOS technology. The purely digital circuit is based on a 2.5 V bipolar-CML static divider, AND gates and inverter stages, and operates with input signals from DC to 124 GHz while consuming 178 mW. Measurements were conducted with 63-GHz and 100-GHz bandwidth real-time oscilloscopes. The measured self-oscillation frequency of the static divider in the generator was 98.8 GHz, compared to 93 GHz in simulation. The measured output signals remained in quadrature up to 62 GHz. The measured duty cycle is 25–26% up to 30 GHz and increases up to 33% at 50 GHz, beyond which measurements are impacted by the limited bandwidth of the oscilloscope. The simulated duty cycle was lower than 28% up to 62 GHz.

A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator

Abstract: This paper presents a power-efficient 10-bit SAR ADC. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain under a low power supply voltage, thereby reducing noise and offset. Statistical estimation and loading switching techniques are synergically combined to further improve the energy efficiency. Moreover, the SAR sequencer and clock generator share only a single dynamic DFF chain to reduce the digital power. A 40nm CMOS prototype achieves a Walden FoM of 1.5fJ/conversion-step while operating at 100kS/s from a 0.5V supply.

A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation

Abstract: This brief presents a spread-spectrum clock generator (SSCG) based on a subsampling phase-locked loop (SSPLL) by calibrating the spreading ratio. The proposed SSCG has a low jitter performance owing to the low in-band phase noise performance of the SSPLL. To achieve a spread-spectrum clocking, the direct voltage-controlled oscillator modulation method is used owing to the absence of a frequency divider. However, the spreading ratio ( ${\delta }$ ) can be varied by process, voltage, and temperature variations. Automatic calibration technique is proposed for a 5000-ppm spreading ratio at 5 GHz. The proposed SSCG achieves a 21-dB electromagnetic interference reduction, has a −104-dBc/Hz phase noise at 200-kHz offset, and consumes 7 mW and occupies a 0.39-mm2 area in a 65-nm CMOS process.

CW-powered squegging micromechanical clock generator

Abstract: A mechanical circuit has been demonstrated that harnesses squegging to convert −50dBm of input continuous-wave (CW) energy into a local 1-kHz clock output while consuming three orders less local battery power than a typical real-time clock (RTC). Unlike a previous clock receiver that relied on a modulated RF input, this clock generator converts a CW input — no modulation needed — to a clock output via squegging of an impacting micromechanical resonant switch (“resoswitch”). Here, impact-induced disruption compels the device's resonating element to lose oscillation amplitude (hence stop impacting), then recover to impact again, only to again lose amplitude, in a periodic and repeatable fashion. The resulting time domain waveform, with periodic peaks and valleys, then provides a stable frequency that serves as a local on-board clock for low data rate applications. By dispensing with the need for a positive feedback sustaining amplifier, this CW-powered mechanical clock generator operates with only 0.8nW of battery power when outputting a triangle-wave into 0.8pF, which is 1250× lower than the μW of a typical RTC.

Asynchronous clock generation for time-interleaved successive approximation analog to digital converters

Abstract: A clock generator (500) includes: a first input (502) to receive a global clock signal (216); a second input (504) to receive a completion signal (516); and a third input (506) to receive differential outputs (116, 312, 314) in a conversion cycle from a comparator (212) The clock generator (500) also includes a logic circuit (508) configured to generate a control clock signal (226) based at least in part on the global clock signal (216) and the differential outputs (116, 312, 314), and to provide the control clock signal (226) to the comparator (212) for a next conversion cycle The logic circuit (508) is also configured to disable the control clock signal (226) in response to the completion signal (516) indicating a completion of required conversion cycles in a conversion phase

Switched-capacitor filter design for ECG application using 180nm CMOS technology

Abstract: This Paper proposes second order switched capacitor filters for ECG application. ECG signal contains different types of noise and artifacts thereby giving rise to the need for signal filtering. Thus a switched capacitor highpass filter withcutoff frequency 0.05Hz and a low pass filterwith cutoff frequency 150Hz are presented. The circuits consist of two phase clock generator, gain stage and switched capacitors. These circuits are designed in Cadence Virtuoso Analog Design Environment using SCL (semi-conductor laboratory) 180nm technology.

Driver module for mach zehnder modulator

Abstract: A single chip dual-channel driver for two independent traveling wave modulators. The driver includes two differential pairs inputs per channel respectively configured to receive two digital differential pair signals. The driver further includes a two-bit DAC per channel coupled to the two differential pairs inputs to produce a single analog differential pair PAM signal at a differential pair output for driving a traveling wave modulator. Additionally, the driver includes a control block having internal voltage/current signal generators respective coupled to each input and the 2-bit DAC for providing a bias voltage, a tail current, a dither signal to assist modulation control per channel. Furthermore, the driver includes an internal I2C communication block coupled to a high-speed clock generator to generate control signals to the control block and coupled to host via an I2C digital communication interface.

High-precision multi-phase clock correcting circuit

Abstract: The invention discloses a high-precision multi-phase clock correcting circuit, belonging to the field of analog integrated circuit technology, and particularly relating to a multi-phase clock phase error correction circuit. The high-precision multi-phase clock correcting circuit disclosed by the invention aims to solve the problem that the existing traditional multi-phase clock generator has clock delay errors due to non-ideal effects; a traditional multi-phase clock generation circuit generates a multi-phase clock by using a multi-level delay chain, and errors are caused by the mismatch between the delay units; and the high-precision multi-phase clock correcting circuit is beneficial to reduce the power consumption and save the chip area, is high in clock phase detection precision and easy to implement, is high in adjustment precision of the clock delay units, adopts the code values of digital codes to correspond to the delay size, ensures that the clock accuracy of the clock correction module depends on the feedback adjustment accuracy and the detection accuracy of the clock phase errors, and ensures that the high-precision multi-phase clock can be achieved.

Clock generation circuit having over-current protecting function, method of operating the same and display device

Abstract: A clock generation circuit includes: a clock generator to receive a gate pulse signal and to generate at least one gate clock signal corresponding to the gate pulse signal; an over-current protector to detect a current level of the at least one gate clock signal, and to output a shutdown enable signal and at least one switching signal corresponding to the detected current level; and a switching unit including at least one switching device to output the gate pulse signal as the at least one gate clock signal. The clock generator is to generate the at least one gate clock signal in response to the shutdown enable signal, and the at least one switching device is to transmit the gate pulse signal as the at least one gate clock signal in response to the at least one switching signal.

A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET

Abstract: This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low-complexity control logic suitable for high-speed applications. Multi-phase clock signals that drive data/edge slicers are created by an open loop quadrature clock generator. The circuit, characterized in an 850nm VCSEL based optical link, recovers PRBS7 data (BER pp at −5dBm optical modulation amplitude (OMA). The RX energy efficiency is 1.9pJ/bit.

PSRR measurement method for PLL including power delivery network

Abstract: A measurement method to estimate PSRR (Power Supply noise Rejection Ratio) of PLL (Phase Locked Loop) using DPI (Direct Power Injection) method is proposed. The DPI (Direct Power Injection) method specified in IEC 62132-4. Through DPI measurement, PLL showed 50 dB to 60 dB PSRR in the 100 kHz ∼ 20 MHz. The power noise level allowed by the DUT is predicted using the PSRR results. The phase noise was measured at various power sources such as LDO and DC-DC converters. These power noise levels are compared with allowable noise specification. PSRR level was improved with 1uF decoupling capacitor by 40dB in the range of 1 MHz ∼ 10 MHz. The proposed method can provide guidelines on selecting a power source component of a clock generator and designing an efficient PDN (Power Delivery Network) structure.

Analog-to-digital converter

Abstract: The invention discloses an analog-to-digital converter, comprising a digital-to-analog converter used for obtaining input signals and outputting the input signals to a comparator; the comparator used for comparing the voltages of the input signals to produce a comparison result, and outputting the comparison result to a sequential pulse generator and an asynchronous successive approximation register; the sequential pulse generator used for generating a first control signal according to the comparison result, generating a plurality of first output signals, outputting the first output signals to the asynchronous successive approximation register and outputting the first output signal with the lowest bit and the first control signal to a comparison clock generator; the asynchronous successive approximation register used for generating a plurality of second output signals according to the comparison result and the first output signals and outputting and latching the second output signals as last results; and the comparison clock generator used for performing OR operation on a sampling clock signal, the first control signal and the first output signal with the lowest bit to generate a comparison clock signal The analog-to-digital converter disclosed by the invention can solve the problem the problem of over low conversion speed of the traditional analog-to-digital converters

Frequency acquisition technique for injection-locked clock generator using asynchronous-sampling frequency detection

Abstract: An injection-locked clock generator with a frequency acquisition scheme, which eliminates a conflict between the injection and the frequency acquisition loop is described. In the proposed frequency detector (FD), the oscillator clock is sampled by the reference clock, which, respectively, becomes asynchronous sampling and synchronous sampling before and after injection locking. By taking advantage of this aspect, the proposed FD does not generate any active output once the oscillator is injection-locked, and therefore the conflict is completely resolved. Moreover, it is not turned off but just produces no output, hence it can immediately react to a sudden loss of injection-locking. The FD is implemented with a low hardware overhead of only six flip-flops and a few logic gates. The validity of the feasibility of the proposed scheme is verified by a circuit simulation.

A 2-4 GHz fast-locking frequency multiplying delay-locked loop

Abstract: A fast-locking fractional-ratio multiplying DLL (FMDLL) for de-skewed on-chip clock frequency multiplication is presented. A new phase detecting controller (PDC) and a dual-path charge pump (CP) have been adopted to achieve shorter locking time and eliminate lock-in fail problems. The proposed fast-locking FMDLL was implemented in a 65-nm CMOS process and occupies an active area of 0.015mm2. It operates over a frequency range of 2.0–4.0GHz with a programmable frequency multiplication factor of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves a peak-to-peak output clock jitter of 13.5 ps at 4GHz while consuming 6.7mW at 2GHz from a 1.2V supply. Compared with the conventional architecture, the locking time has been reduced about 80%.

Spread spectrum clock signal generator

Abstract: The utility model relates to a spread spectrum clock signal generator. Spread spectrum clock signal generator includes: a clock generator, the frequency that clock generator is used for using modulating signal to come modulation reference clock signal is in order to provide spread spectrum clock signal, clock generator has characteristic transfer function, and modulator, the modulator is used for generating according to expectation distribution curve modulating signal, the expectation distribution curve be through clock generator characteristic transfer function's inverse function is adjusted. The utility model provides a technical problem prevent because the maloperation that leads to of high -caliber electromagnetic interference. The utility model discloses a technological effect is the electromagnetic interference who reduces to influence the circuit.

Supply voltage droop management circuits for reducing or avoiding supply voltage droops

Abstract: Supply voltage droop management circuits for reducing or avoiding supply voltage droops are disclosed. A supply voltage droop management circuit includes interrupt circuit configured to receive event signals generated by a functional circuit. Event signals correspond to an operational event that occurs in the functional circuit and increases load current demand to a power supply powering the functional circuit, causing supply voltage droop. The interrupt circuit is configured to generate an interrupt signal in response to the received event signal. Memory includes an operational event-frequency table having entries with a target frequency corresponding to an operational event. Operating the functional circuit at target frequency reduces the load current demand on the power supply, and supply voltage droop. A clock control circuit is configured to receive interrupt signal, access memory to determine the target frequency, and generate clock frequency adjustment signal to cause clock generator to adjust to the target frequency.

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel

Abstract: A 1.62-to-8.1 Gb/s video interface receiver with an adaptive equalizer and a stream clock generator (SCG) is proposed. The adaptation logic is achieved by an edge-based adaptation and it controls the continuous-time linear equalizer ac boost. Using the adaptation logic, the minimum BER point is selected for several cables. The SCG consists of a phase-switching fractional divider and a delta–sigma modulator. The dividing factor is determined by the display resolution and the SCG operates up to 680 MHz which is the 4K UHD pixel frequency. The proposed receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.282 mm2. The measured BER is less than $10^{-12}$ with a 20-ft-long video cable, whose insertion loss at 4.05 GHz is 20 dB. The receiver consumes 55.1 mW at the data rate of 8.1 Gb/s.

Display device having gate driving circuit and driving method thereof

Abstract: A display device includes: a display panel; a voltage generator to output a gate on voltage to a voltage output terminal; a clock generator to receive the gate on voltage to generate at least one clock signal; a gate driving circuit including a plurality of driving stages to output gate signals to gate lines in response to the at least one clock signal, each of the driving stages including at least one transistor to adjust a threshold voltage based on a back bias control voltage; and a signal controller to detect a current variation of the voltage output terminal and including a back bias controller to search for the back bias control voltage to minimize a consumption current level of the voltage output terminal while changing the back bias control voltage from a default voltage level when the detected current variation is greater than a reference level.

System and method for associative power and clock management with instruction governed operation for power efficient computing

Abstract: A system includes an ARM core processor, a programmable regulator, a compiler, and a control unit, where the compiler uses a performance association outcome to generate a 2-bit regulator control values encoded into each individual instruction. The system can provide associative low power operation where instructions govern the operation of on-chip regulators or clock generator in real time. Based on explicit association between long delay instruction patterns and hardware performance, an instruction based power management scheme with energy models are formulated for deriving the energy efficiency of the associative operation. An integrated voltage regulator or clock generator is dynamically controlled based on instructions existing in the current pipeline stages leading to additional power saving. A compiler optimization strategy can further improve the energy efficiency.

Power Output Circuit And Related Control Method

Abstract: The invention discloses a power output circuit and a related control method. A power output circuit includes a charge pump, a voltage regulator, a clock generator and a voltage detector. The charge pump is used for receiving a clock signal having an operating frequency and outputting an output voltage. The voltage regulator, coupled to the charge pump, is used for outputting a control voltage to the charge pump, to control the output voltage. The clock generator, coupled to the charge pump, is used for outputting the clock signal to the charge pump. The voltage detector, coupled to the clock generator and the voltage regulator, is used for detecting the control voltage and controlling the clock generator to adjust the operating frequency of the clock signal according to a magnitude of the control voltage.

Signal analysis and phantom experiments for a miniaturized time-domain microwave breast health monitoring device

Abstract: This work presents a miniaturized system for performing time-domain microwave scans to detect malignancies within breast tissue The proposed changes miniaturize components of the system designed by the McGill Breast Cancer Detection Group The aim of this paper is to present the implementation of the Adafruit Si5351 Clock Generator and the Furaxa Pulser as an alternative to the currently used large table-top and expensive Tektronix gigaBERT 1400 Clock Generator and Picosecond Model 3600 Impulse Generator respectively The miniaturized and cost-effective components can be integrated to achieve a comfortable and compact medical imaging device This paper validates the proposed changes to the system by comparing their signals at the relevant stages of the system Moreover, a dataset is collected with the proposed system changes using realistic breast phantoms across a five day period