Showing papers on "Decoupling capacitor published in 2003"

Drive method of el display panel

Abstract: A switching transistor is controlled to turn on or off depending on a turn-on voltage or a turn-off voltage applied to a gate signal line. A driver transistor is supplied with an image signal applied to a source signal line through a switching transistor. A voltage based on the supplied image signal is retained by a capacitor. The driver transistor supplies a light-emitting current to an EL element based on the voltage retained in the capacitor. A capacitor is formed between one terminal of the capacitor (that is, a gate terminal of the driver transistor) and a gate signal line. The capacitor causes the gate terminal voltage of the driver transistor to be varied depending on variation of the potential on the gate signal line.

Photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured with the same

Abstract: A photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured by the same are disclosed. The photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by analyzing a pattern in a mask layout file to identify a region in the pattern to add one or more decoupling capacitors. Once the region is identified, a feature located in the identified region is moved based on a design rule from a first position to a second position in the mask layout file to create a space in the identified region. The decoupling capacitors are placed in the space in the identified region.

Dielectric nanocomposites for integral thin film capacitors: materials design, fabrication and integration issues

Abstract: Nanocomposites of organically modified barium titanate (BTO) nanoparticles in an epoxy matrix have been synthesized and evaluated as dielectrics for the fabrication of integral thin film capacitor arrays. Organic modification of the polymer inorganic interface has been used as a design tool to control the cross link density of the polymeric matrix and the interfacial interactions. Impedance spectra generated with model networks has been employed to analyze the experimental data and to model the role of the ceramic core, interface and the polymer matrix in determining the dielectric behavior of the nanocomposites. Stealth decoupling capacitor arrays were fabricated employing BTO-Epoxy nanocomposite thin films as dielectric layer. Capacitor arrays were fabricated by patterning the top electrode in the glass/Al/BTO-epoxy/spl bsol/Al heterostructures employing a photolithographic process and their electrical performance characterized. The role of an organically modified interface in limiting the thermal diffusion of copper metal in the composite thin film has been investigated employing Rutherford backscattering spectroscopy.

Optimal decoupling capacitor sizing and placement for standard-cell layout designs

Abstract: With technology scaling, the trend for high-performance integrated circuits is toward ever higher operating frequency, lower power supply voltages, and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the 2001 International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. In this paper, we propose and demonstrate an algorithm for the automated placement and sizing of decaps in application specific integrated circuit (ASIC)-like circuits. The problem is formulated as one of nonlinear optimization and is solved using a sensitivity-based quadratic programming (QP) solver. The adjoint sensitivity method is applied to calculate the first-order sensitivities. We propose a fast convolution technique based on piecewise linear (PWL) compressions of the original and adjoint waveforms. Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change in the total chip area.

Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device

Abstract: It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.

Integrated broadband ceramic capacitor array

Abstract: A monolithic capacitor structure includes opposed and overlapping plates within a dielectric body, which are arranged to form a lower frequency, higher value capacitor Other conductive structure is located either inside the dielectric body or on an external surface thereof and is effective to form a higher frequency, lower value capacitor in parallel with the lower frequency, higher value capacitor The resulting array of combined series and parallel capacitors integral with the dielectric body provides effective wideband performance in an integrated, cost-effective structure

Ground bounce in digital VLSI circuits

Abstract: This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.

Predictive DC voltage control of single-phase PV inverters with small DC link capacitance

Abstract: This paper proposes a novel control method for DC voltage in single-phase voltage-source inverters fed by constant-current or constant-power sources. The technique predicts the inverter power require to correct a DC voltage error within one fundamental AC cycle. This is based on the power balance between DC input and AC output, and the energy stored in the DC link capacitor. The fast response means a smaller capacitor can be used, and operation with a large double-line-frequency ripple on the DC bus is possible without causing distortion of the AC output current. This scheme is suitable for applications where substantial DC link buffer energy is unnecessary, e.g.: grid-connected photovoltaic generators. The reliability and lifetime of the inverter can be significantly improved if a non-electrolytic type capacitor is used. Experimental results are presented that verify the inverter operation.

Power-bus decoupling with embedded capacitance in printed circuit board design

Abstract: This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).

Boost converter with high voltage gain using a switched capacitor circuit

Abstract: An integrated boost switched-capacitor (SC) converter able to step-up the line by ten times is presented. It is formed by a SC-circuit containing three capacitors and a boost stage. The two power stages are not connected in cascade, but they are integrated for achieving an overall high efficiency. The SC-circuit allows for a steep voltage ratio; for efficiency's purpose, it is not regulated. The boost stage gives the line and load regulation, using a classical PWM control. The theoretical results based on an energy-balance approach and simulation using the exact cyclical differential equations of the converter are confirmed by the experimental results on a prototype of 35 W power.

Charge pump-type booster circuit

Abstract: A charge pump-type booster circuit can reduce numbers of switches and capacitors. The charge pump-type booster circuit has a first electronic switch and a second switch connecting a high potential terminal and a low potential terminal of a charge capacitor are connected to a not grounded terminal of a first output capacitor connected to the ground at one side. These electronic switches are not conducted simultaneously. A third electronic switch is provided for connecting the high potential terminal of the charge capacitor and a not grounded terminal of a second output capacitor grounded at one side.

Multiple chips bonded to packaging structure with low noise and multiple selectable functions

Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.

MIM capacitors and methods for fabricating same

Abstract: Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another, wherein the capacitor segments may be connected in reverse polarity relationship to provide symmetrical performance characteristics for the analog capacitors.

Power Distribution Networks in High Speed Integrated Circuits

Abstract: 1. Introduction.- 1.1 Evolution of integrated circuit technology.- 1.2 Evolution of design objectives.- 1.3 The problem of power distribution.- 1.4 Deleterious effects of power distribution noise.- 1.4.1 Signal delay uncertainty.- 1.4.2 On-chip clock jitter.- 1.4.3 Noise margin degradation.- 1.4.4 Degradation of gate oxide reliability.- 1.5 Book outline.- 2. Inductive Properties of Electric Circuits.- 2.1 Definitions of inductance.- 2.1.1 Field energy definition.- 2.1.2 Magnetic flux definition.- 2.1.3 Partial inductance.- 2.1.4 Net inductance.- 2.2 Variation of inductance with frequency.- 2.2.1 Uniform current density approximation.- 2.2.2 Inductance variation mechanisms.- 2.2.3 Simple circuit model.- 2.3 Inductive behavior of circuits.- 2.4 Inductive properties of on-chip interconnect.- 2.5 Summary.- 3. Properties of On-Chip Inductive Current Loops.- 3.1 Introduction.- 3.2 Dependence of inductance on line length.- 3.3 Inductive coupling between two parallel loop segments.- 3.4 Application to circuit analysis.- 3.5 Summary.- 4. Electromigration.- 4.1 Physical mechanism of electromigration.- 4.2 Electromigration-induced mechanical stress.- 4.3 Steady state limit of electromigration damage.- 4.4 Dependence of electromigration lifetime on the line dimensions.- 4.5 Statistical distribution of electromigration lifetime.- 4.6 Electromigration lifetime under AC current.- 4.7 Electromigration in novel interconnect technologies.- 4.8 Designing for electromigration reliability.- 4.9 Summary.- 5. High Performance Power Distribution Systems.- 5.1 Physical structure of a power distribution system.- 5.2 Circuit model of a power distribution system.- 5.3 Output impedance of a power distribution system.- 5.4 A power distribution system with a decoupling capacitor.- 5.4.1 Impedance characteristics.- 5.4.2 Limitations of a single-tier decoupling scheme.- 5.5 Hierarchical placement of decoupling capacitance.- 5.6 Resonance in power distribution networks.- 5.7 Full impedance compensation.- 5.8 Case study.- 5.9 Design considerations.- 5.9.1 Inductance of the decoupling capacitors.- 5.9.2 Interconnect inductance.- 5.10 Limitations of the one-dimensional circuit model.- 5.11 Summary.- 6. On-Chip Power Distribution Networks.- 6.1 Styles of on-chip power distribution networks.- 6.1.1 Basic structure of on-chip power distribution networks.- 6.1.2 Improving the impedance characteristics of on-chip power distribution networks.- 6.1.3 Evolution of power distribution networks in Alpha microprocessors.- 6.2 Allocation of on-chip decoupling capacitance.- 6.2.1 Types of on-chip decoupling capacitance.- 6.2.2 Allocation strategies.- 6.2.3 On-chip switching voltage regulator.- 6.3 Die-package interface.- 6.4 Other considerations.- 6.5 Summary.- 7. Computer-Aided Design and Analysis.- 7.1 Design flow for on-chip power distribution networks.- 7.2 Linear analysis of power distribution networks.- 7.3 Modeling power distribution networks.- 7.4 Characterizing the power current requirements of on-chip circuits.- 7.5 Numerical methods for analyzing power distribution networks.- 7.6 Summary.- 8. Inductive Properties of On-Chip Power Distribution Grids.- 8.1 Power transmission circuit.- 8.2 Simulation setup.- 8.3 Grid types.- 8.4 Inductance versus line width.- 8.5 Dependence of inductance on grid type.- 8.5.1 Non-interdigitated versus interdigitated grids.- 8.5.2 Paired versus interdigitated grids.- 8.6 Dependence of Inductance on grid dimensions.- 8.6.1 Dependence of inductance on grid width.- 8.6.2 Dependence of inductance on grid length.- 8.6.3 Sheet inductance of power grids.- 8.6.4 Efficient computation of grid inductance.- 8.7 Summary.- 9. Variation of Grid Inductance with Frequency.- 9.1 Analysis approach.- 9.2 Discussion of inductance variation.- 9.2.1 Circuit models.- 9.2.2 Analysis of inductance variation.- 9.3 Summary.- 10. Inductance/Area/Resistance Tradeoffs.- 10.1 Inductance vs. resistance tradeoff under a constant grid area constraint.- 10.2 Inductance vs. area tradeoff under a constant grid resistance constraint.- 10.3 Summary.- 11. Scaling Trends Of On-Chip Power Distribution Noise.- 11.1 Prior work.- 11.2 Interconnect characteristics.- 11.2.1 Global interconnect characteristics.- 11.2.2 Scaling of the grid inductance.- 11.2.3 Flip-chip packaging characteristics.- 11.2.4 Impact of on-chip capacitance.- 11.3 Model of power supply noise.- 11.4 Power supply noise scaling.- 11.4.1 Analysis of constant metal thickness scenario.- 11.4.2 Analysis of the scaled metal thickness scenario.- 11.4.3 ITRS scaling of power noise.- 11.5 Implications of noise scaling.- 11.6 Summary.- 12. Impedance Characteristics of Multi-Layer Grids.- 12.1 Electrical properties of multi-layer grids.- 12.1.1 Impedance characteristics of individual grid layers.- 12.1.2 Impedance characteristics of multi-layer grids.- 12.2 Case study of a two layer grid.- 12.2.1 Simulation setup.- 12.2.2 Inductive coupling between grid layers.- 12.2.3 Inductive characteristics of a two layer grid.- 12.2.4 Resistive characteristics of a two layer grid.- 12.2.5 Variation of impedance with frequency in a two layer grid.- 12.3 Design implications.- 12.4 Summary.- 13. Inductive Effects In On-Chip Power Distribution Networks.- 13.1 Scaling effects in chip-package resonance.- 13.2 Propagation of power distribution noise.- 13.3 Local inductive behavior.- 13.4 Summary.- 14. Conclusions.- References.- About the Authors.

Circuit for starting power source apparatus

Abstract: When an AC power source ( 1 ) is turned on, energy is accumulated in a backup capacitor ( 63 ) by an energy supply circuit ( 64 ). An internal power source ( 65 ) supplies the energy accumulated in the capacitor ( 63 ) to a control unit ( 49 ). Thus, a power factor improvement circuit ( 40 - 2 ) operates. When the power factor improvement circuit ( 40 - 2 ) operates to output a predetermined voltage, an output voltage detection circuit ( 67 ) detects the voltage, and switches the internal power source ( 66 ) on. The turned on internal power source ( 66 ) supplies the energy in the capacitor ( 63 ) to a control unit ( 56 ) to operate a DC/DC conversion circuit ( 50 ). In this way, by operating the DC/DC conversion circuit ( 50 ) after operating the power factor improvement circuit ( 40 - 2 ), the capacity of the capacitor ( 63 ) can be reduced.

Analysis of IR-drop scaling with implications for deep submicron P/G network designs

Abstract: This paper presents a detailed analysis of the power-supply voltage (IR) drop scaling in DSM technologies. For the first time, the effects of temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the IR-drop effect in the power/ground (P/G) network increases rapidly with technology scaling, and using well-known counter measures such as wire-sizing and decoupling capacitor insertion with resource allocation schemes that are typically used in the present designs may not be sufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power lines of switching devices in a clock network can introduce significant amount of skew which in turn degrades the signal integrity.

Integrated start-up circuit with reduced power consumption

Abstract: A switching power supply control-circuit according to the present invention uses bleeding resistors to charge a start-up capacitor and discharge an EMI filter. No extra discharge device is needed to accelerate the discharge of the input capacitor, since the start-up capacitor is charged up by the AC input source. A latch circuit of the power supply can be quickly reset after the AC input source is shut off. After the control-circuit begins to operate, the auxiliary winding of the transformer will power the control-circuit. To further reduce power consumption, the auxiliary winding generates a bias voltage to enable line-voltage detection. This allows the power supply to perform line-voltage detection and startup, without having to connect resistors or transistors to the input capacitor.

RFID tag and method for processing RFID data

Abstract: A collision prevention relational function is disclosed for RFID tags, which increases stability during system operations. The RFID tag includes a parallel resonance circuit having a coil, a resonance capacitor, an adjustment capacitor, a switching circuit, a rectification circuit, a smoothing capacitor, a constant-voltage circuit, a voltage detection circuit, an exclusive OR circuit, a timer circuit, a voltage detection circuit, a control circuit, an OR circuit, a latch circuit, an UID storage device, and a data modulator/demodulator. When a predetermined power supply voltage/operating voltage is obtained, an anti-collision algorithm identifies and adjusts RFID tags that experienced collision.

High peak power plasma pulsed supply with arc handling

Abstract: There is provided by this invention novel magnetron sputtering apparatus that is generally comprised of a pulsed do power supply capable of delivering peak powers of 0.1 megaWatts to several megaWatts with a peak power density greater than 1 kW/cm2. The power supply has a pulsing circuit comprised of an energy storage capacitor and serially connected inductor with a switching means for disconnecting the pulsing circuit from the plasma and recycling the inductor energy back to the energy storage capacitor at the detection of an arc condition. The energy storage capacitor and the serially connected inductor provide an impedance match to the plasma, limits the current rate of rise and peak magnitude in the event of an arc, and shapes the voltage pulses to the plasma.

Luminescence display device and method for driving display panel of the display device

Abstract: PROBLEM TO BE SOLVED: To provide a luminescence display device capable of compensating the threshold voltage and movement of transistors and sufficiently charging a data line. SOLUTION: A driving transistor for outputting a current for driving an organic electroluminescence (EL) element is formed in each pixel circuit of the organic EL display device. A 1st capacitor is connected between power supply voltage and the gate of the driving transistor and a 2nd capacitor is connected to the gate of the driving transistor and a scanning line. Voltage corresponding to a data current is stored in the 1st capacitor in response to a selection signal from the scanning line. The voltage of the 1st capacitor is changed when the level of the selection signal is changed. A driving current is outputted from the transistor by the changed voltage of the 1st capacitor and each organic EL element is emitted by the driving current. Thus the current flowing into the organic EL element as a large data current can be controlled. COPYRIGHT: (C)2004,JPO

A simple finite-difference frequency-domain (FDFD) algorithm for analysis of switching noise in printed circuit boards and packages

Abstract: Simultaneous switching noise (SSN) compromises the integrity of the power distribution structure on multilayer printed circuit boards (PCB). Several methods have been used to investigate SSN. These methods ranged from simple lumped circuit models to full-wave (dynamic) three-dimensional Maxwell equations simulators. In this work, we present an efficient and simple finite-difference frequency-domain (FDFD) based algorithm that can simulate, with high accuracy, the capacity of a PCB board to introduce SSN. The FDFD code developed here also allows for simulation of real-world decoupling capacitors that are typically used to mitigate SSN effects at sub 1 GHz frequencies. Furthermore, the algorithm is capable of including lumped circuit elements having user-specified complex impedance. Numerical results are presented for several test boards and packages, with and without decoupling capacitors. Validation of the FDFD code is demonstrated through comparison with other algorithms and laboratory measurements.

Circuits and techniques for capacitor charging circuits

Abstract: The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

Circuit and a method for controlling the bias current in a switched capacitor circuit

Abstract: A tunable constant GM circuit allows to compensate for temperature and process variations with high precision by correspondingly adjusting a resistance value and/or the ratio of transistor widths. Thus, in switched capacitor circuits the frequency behaviour, such as the settling time, may be controlled by providing a compensated bias to the transconductance amplifiers typically used in these circuits.

Hybrid power supply system

Abstract: It is an object of the present invention to provide a high efficiency hybrid power supply system that permits a power type power supply device such as a capacitor to be utilized effectively, and that makes it possible to even the burden on an energy type power supply device such as a storage cell. A capacitor 21 is connected to system voltage lines 26 and 27 which are connected to a load 30 , and a body formed by a serial connection between a large-capacity storage cell 22 and the output terminal of a voltage controller 23 is connected in parallel with this capacitor 21 . The voltage Vb of the storage cell 22 is substantially constant. The voltage controller 23 is a DC/DC converter, for example, the output voltage Vv of which is variable. A system controller 25 changes the system voltage Vs by changing the output voltage Vv of the voltage controller 23 . When a large amount of electric power is to be supplied to the load 30 , energy is rapidly discharged from the capacitor 21 and supplied to the load 30 by lowering the system voltage Vs. When a large amount of electric power is to be fed back from the load 30 , energy from the load 30 is rapidly absorbed by the capacitor 21 by raising the system voltage Vs.

Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise

Abstract: While circuit and package designers have addressed microprocessor inductive noise issues in the past, multi-gigahertz clock frequencies and billion-transistor-level integration are exacerbating the problem, necessitating microarchitectural solutions. The large net on-die decoupling capacitance used to address this noise throughout the chip consumes substantial area and can cause a large leakage current. This paper proposes microarchitectural techniques to reduce high-frequency current variability, reducing the need for decoupling capacitors. We observe that we can control inductive noise by reducing current variability either in space (i.e., variability in usage of circuit blocks) or in time (i.e., variability within a circuit block across clock cycles). We propose pipeline muffling, a novel technique to reduce changes in the number of resources being utilized by controlling instruction issue, trading off some energy and performance to control di/dt in space. We also extend a previous technique, which incurs performance and energy degradation, and propose a priori current ramping to allow the current of a resource to ramp up ahead of usage, with virtually no performance loss, and ramp down immediately after usage, with little energy loss. Our techniques guarantee a worst-case bound on the di/dt, which is required to reduce the demand for decoupling capacitors, saving area and reducing leakage.

Dual bridge matrix converter

Abstract: A dual bridge matrix converter has a line-side converter with controllable switches that receives AC power and provides unidirectional power to high and low DC link lines, and a load-side converter which receives the power from the DC link lines and provides AC power to output lines. A clamp circuit is connected across the DC link lines and includes a series connected diode and a capacitor. Negative DC link current will be conducted through the clamp diode to charge the clamp capacitor to avoid voltage spikes on the DC link lines. A controllable switch may be connected in parallel with the clamp diode and is turned on when the voltage across the clamp capacitor is above a threshold that is greater than the normal peak-to-peak AC input voltage. The switch is turned off when the voltage across the clamp capacitor is lower than the threshold voltage.

Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage

Abstract: Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause noise margins to decrease, while increasing current and frequency makes supply noise injection larger, especially noise caused by inductance in the supply lines. Creating power distribution systems is one of the key challenges in modern chip design. Decoupling capacitance helps reduce inductance effects, but there is often a peak in the supply impedance that occurs at a resonant frequency caused roughly by the package inductance and the chip decoupling capacitors. This frequency is on the order of 100MHz, which is much lower than the operating frequency of the processor. We propose pipeline damping, an architectural technique which controls instruction issue to guarantee bounds on current variation around the frequency of the supply resonance, thus reducing the resulting supply noise. Damping is a cheaper alternative to expensive, circuit-based noise-reduction techniques. We make the fundamental observation that limiting the current flow change (di) within resonant time period (dt) controls di/dt without large performance loss. Damping guarantees bounds on current variation while allowing processor current to increase or decrease to the magnitude required to maintain performance. Our results show that a damped processor guarantees a 33% reduction in the worst-case current variation with an average performance degradation of 7% and average energy delay of 1.09 compared to an undamped processor.

High precision analog to digital converter

Abstract: An analog to digital converter (ADC) includes a cross switch array coupled between an input switch array and an integrator configured to alternately transfer charges from a first input capacitor and a second input capacitor to a first integration capacitor and a second integration capacitor thereby improving linearity problems caused by capacitor mismatching. The cross switch array may also be configured to transfer charges from the first input capacitor to the first integration capacitor and from the second input capacitor to the second integration capacitor during a first charge transfer time interval, and from the first input capacitor to the second integration capacitor and from the second input capacitor to the first integration capacitor during a second charge transfer time interval. A sensing system including and ADC consistent with the invention is also provided. Various methods of transferring charges in an ADC are also provided.

Non-intrusion type charging system for artificial organ, capacitor and power supplying device used in the system

Abstract: A non-intrusion type charging device for a secondary battery for driving a heart pace maker by a non-contact induction power supply. A plurality of direction detection coils arranged in an annular shape detect a positional shift between a power transmission coil (9) and a power reception coil (4). The coil position shift information and information on charge voltage of an electric double-layer capacitor (6) are transmitted by a pulse signal to a primary side control circuit (15) outside a human body and displayed on a charge state display panel (16) and a coil shift amount display panel (18).

Battery power circuit

Abstract: There is provided a battery power circuit capable of preventing lowering of power supply to a motor at start and obtaining a predetermined engine rpm even if an idle stop operation is performed continuously. The battery power circuit includes a battery (1) connected to a load (not depicted) as an object to which power is supplied, a series-connected power source having a capacitor group (2) connected in series, a DC/DC converter (3) for transferring power between the battery (1) and the capacitor group (2) and between the battery (1) and the load, and a control device (5) for controlling the DC/DC converter (3). The control device (5) detects voltage of the capacitor group (2). If the voltage detected is smaller than a first threshold value (for example, 4.0 V), the capacitor group (2) is charged by the DC/DC converter (3).