Showing papers on "Field-effect transistor published in 1976"

The use of charge pumping currents to measure surface state densities in MOS transistors

Abstract: A method is described for determining the surface-state density at the oxide interface in the channel of an MOS transistor from the charge pumping current flowing to the substrate when gate pulses are applied. From this simple measurement the surface state density can be determined as a function of gate voltage and if a quasi-static C-V characteristic is also measured for the gate of the transistor then the voltage distribution can be converted into an energy distribution. Representative results obtained on a set of commercial transistors show a large increase in the surface-state density near the middle of the band-gap after negative-bias thermal-stressing.

Field effect transistor for detection of biological reactions

Abstract: A field effect transistor including conventional source and drain electrodes employs, in the gate region, a layer of antibody specific to a particular antigen. An electrolyte solution such as 0.155 Normal sodium chloride atop the antibody layer provides a predetermined drain current versus drain voltage characteristic for the device. Replacement of the electrolyte solution with another electrolyte solution containing the antigen alters the charge of the protein surface layer due to the antigen-antibody reaction, thus affecting charge concentration in a semiconductor inversion layer in the transistor. The time rate of change of drain current thus provides a measure of the antigenic protein concentration in the replacement solution.

Two-dimensional numerical analysis of stability criteria of GaAs FET's

Abstract: Stability criteria of GaAs junction-gate FET's are studied by two-dimensional numerical analysis. The analysis covers the wide range of device geometry from the state of the art FET to the so-called Gunn effect digital devices. It is found that a GaAs FET exhibits either of the following three types of characteristics depending upon device geometry and doping concentration. First, for a thin channel with high doping concentration, the device tends to behave as a normal junction-gate FET with saturating current-voltage characteristics. This is even true when the n-l (device length) and n.d (device thickness) products exceed the previously accepted criteria for Gunn oscillation. Second, a stable negative resistance (SNR) is observed in devices with a moderate channel thickness. Third, for a thick channel, the device exhibits a Gunn oscillation with the domain propagating from the gate edge to the drain. These three categories of behavior are mapped on the nd plane with the help of simple analytic considerations. The map is found to compare well with experimental results.

Two-dimensional carrier flow in a transistor structure under nonisothermal conditions

Abstract: A two-dimensional mathematical model is developed to predict the internal behavior of power transistors operating under steady-state conditions. This model includes the internal self-heating effects in power transistors and is applicable to predict the transistor behavior under high-current and high-voltage operating conditions. The complete set of partial differential equations governing the bipolar semiconductor device behavior under nonisothermal conditions is solved by numerical techniques without assuming internal junctions and other conventional approximations. Input parameters for this model are the dimension of the device, doping profile, mobility expressions, generation-recombination model, and the boundary conditions for external contacts. Computer results of the analysis of a typical power transistor design are presented for specified operating conditions. The current density, electrostatic potential, carrier charge density, and temperature distribution plots within the transistor structure illustrate the combined effect of the electrothermal interaction, base conductivity modulation, current crowding, base pushout, space charge layer widening, and current spreading phenomena in power transistors.

Simple method of measuring drift-mobility profiles in thin semiconductor films

Abstract: A simple method of measuring drift-mobility profiles in semiconductor films is described. It is based on the low-frequency measurement of the transconductance and gate capacitance of an f.e.t. structure as a function of gate bias. Drift mobilities of 4000 to 5000 cm2/Vs have been measured on n-type GaAs films with 1016 to 1017 cm-3 doping levels.

Threshold voltage of narrow channel field effect transistors

Abstract: A new effect associated with Metal-Oxide-Silicon Field-Effect-Transistors (MOS-FET's) is presented in this paper. MOS-FET's show an increase of threshold voltage with decreasing ratio of channel width to gate depletion width. This narrow channel effect is explained by means of geometrical edge effects. With decreasing channel width the transition from the field oxide depletion region to the gate oxide depletion region becomes comparable to the gate width and cannot be neglected in the derivation of the threshold voltage equation. A theoretical model is given to explain the influence of decreasing channel width on the threshold voltage as well as on other electrical parameters. This theoretical model is in good agreement with experimental results given in this paper.

Monolithic broadband GaAs f.e.t. amplifiers

Abstract: A unique monolithic X-band f.e.t. amplifier is described. Wideband matching circuits, using lumped elements, are integrated with the transistor on semi-insulating gallium arsenide to produce an amplifier chip 1.8×1.2 mm. Gains in excess of 4.5 dB over 7.5 to 11.5 GHz have been measured. The chip has been installed into a low-parasitic package to produce a gain module suitable for the microwave engineer.

A computer-aided design model for high-voltage double diffused MOS (DMOS) transistors

Abstract: High-voltage double diffused metal-oxide semiconductor transistors (DMOST's) have been fabricated with drain-source breakdown voltage greater than 200 V. This paper describes an experimental and theoretical study of the current-voltage behavior of these devices leading to a two-component MOS field effect transistor (MOSFET)-resistor model appropriate for computer-aided circuit design. The effects of velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel, and of spreading resistance in the drift region are considered. Parameter extraction for experimentally characterizing these effects is described. Comparison of experimental and theoretical results shows that the model accurately predicts the device I/V characteristics. The range of validity of the model is limited primarily by high current saturation effects.

Protection circuitry for insulated-gate field-effect transistor (IGFET) circuits

Abstract: The gate insulator of an IGFET, whose gate is connected to the input terminal of a circuit, is protected by limiting the potential difference between any two circuit terminals. Each input and output terminal of the circuit is connected via protective diodes to the power supply lines of the circuit and a high conductivity, low reverse dynamic impedance, diode is connected between the power supply lines. The reverse voltage across the high conductivity diode is less than that of any other diodes at a given current level, whereby only the high conductivity diode conducts substantial currents in the reverse direction.

Avalanche breakdown in high-voltage D-MOS devices

Abstract: A new type of voltage breakdown occurring in high-voltage D-MOS transistors is described. This effect severely reduces the high-voltage capability of these devices when the gate field plate is extended through the drift region toward overlapping the n+drain contact region. The breakdown is shown to be due to an avalanche phenomenon appearing close to the n+region, due to the very high field induced in this NIOS structure in nonequilibrium. A first-order theory is developed to confirm the conclusions of the experimental study.

Uhf tuning circuit utilizing a varactor diode

Abstract: In the UHF tuning portion of a television receiver, a varactor tuned circuit is coupled to the gate electrode of a field effect transistor (FET) through an impedance transformation network comprising a series connected capacitor and shunt connected inductor. In order to increase the signal power transferred between the tuned circuit and the FET at the lower end of the UHF range, the values of the capacitor and inductor are selected so that the relatively low value of equivalent parallel impedance exhibited by the tuned circuit at the lower end of the UHF range is impedance transformed to a value approximately equal to the value of the impedance exhibited at the gate of the FET. A second impedance transformation network, similar to the first, is coupled between the drain of the FET and a second varactor tuned circuit to further increase the signal power transferred between the FET and the second tuned circuit at the lower end of the UHF band. The values of the capacitor and inductor comprising the impedance transformation networks are also selected so that the signal power gain of the UHF tuning portion at the upper end of the UHF range is not substantially degraded. Because of the impedance transformation networks, resonant points below the lowest frequency in the UHF band are established.

Detection of H2S with Pd‐gate MOS field‐effect transistors

Abstract: H2S gas sensitivity of Pd‐gate MOS field‐effect transistors has been studied in air for different temperatures. The possible chemical reactions of H2S and O2 on palladium are discussed.

GaAs microwave power FET

Abstract: A design consideration for an X-band GaAs power FET, features of the fabrication process, and electrical characteristics of the FET are described. Interdigitated 53 source and 52 drain electrodes and an overlaid gate electrode for connecting 104 Schottky gates in parallel have been introduced to achieve a 1.5-µm-long and 5200-µm-wide gate FET. A sheet grounding technique has been developed in order to minimize the common source lead inductance (L 8 = 50 pH). The resulting devices can produce 0.7-W and 1.6-W saturation output power at 10 GHz and 8 GHz, respectively. At 6 GHz, a linear gain of 7 dB, an output power of 0.85 W at 1-dB gain compression and 30-percent power added efficiency can be achieved. The intercept point for third-order intermodulation products is 37.5 dBm at 6.2 GHz.

Protective circuit and device for metal-oxide-semiconductor field effect transistor and method for fabricating the device

Abstract: A protective circuit comprises a metal-oxide-semiconductor field effect transistor (MOSFET) to be protected, and a depletion-type MOSFET the gate and source of which are connected to each other and the souce of which is connected to the gate of the MOSFET to be protected, whereby the protective circuit which is suitable for a high-speed operation is completed.

Externally controlled semiconductor devices with integral thyristor and bridging FET components

Abstract: A semi-conductor device includes a semi-conductor body with four layers of alternate P and N conducting types, these layers constituting a thyristor whose outermost layers form emitter junctions with adjacent layers. The semi-conductor body also includes an integrated field effect transistor part for bridging one of the emitter junctions of the thyristor. The source and drain of the field effect transistor include regions of the same conductivity type, one of which forms the emitter layer adjacent to the bridged emitter junction and the other of which comprises a region ohmically connected to the layer adjacent to the emitter layer and of the same type of conductivity as the emitter layer. The field effect transistor has a control electrode and a protective diode is provided in the semi-conductor body for limiting voltage between the control electrode of the field effect transistor and the semi-conductor body. The thyristor is arranged for optical ignition.

Field-effect transistor

Abstract: PROBLEM TO BE SOLVED: To provide a field-effect transistor for improving high frequency gain characteristics SOLUTION: This field-effect transistor is provided with: an active layer formed on a substrate 10; a source electrode 1 and a drain electrode 3 separately formed on the active layer; a gate electrode 2 formed between the source electrode 1 and the drain electrode 3; a first inter-layer film 21 formed on the active layer; a first FP electrode 5 connected to the gate electrode 2, and arranged on the first inter-layer film 21 in a region between the gate electrode 2 and the drain electrode 3; a second inter-layer film 22 formed on the first inter-layer film 21; and a second FP electrode 6 connected to the source electrode 1, and arranged on the second inter-layer film 22 in a region between the first FP electrode 6 and the drain electrode 3 COPYRIGHT: (C)2009,JPO&INPIT

Power GaAs MESFET with a High Drain-Source Breakdown Voltage

Abstract: A power GaAs MESFET with a high drain-source breakdown voltage in excess of 17 V has been developed. A selective GaAs epitaxial process is introduced to form "inlaid" n+ source and drain regions that can provide a high drain-source breakdown voltage and a low ohmic-contact resistance. Typical characteristics of the MESFET composed of two-cell units are as follows:

Substrate Current due to Impact Ionization in MOS-FET

Abstract: The substrate leakage current vs. gate voltage characteristics of MOS-FET was examined over a wide range of device parameters and measurement conditions. With the increase in the gate voltage, the substrate current increases until it reaches a maximum value. Then it decreases to the value of the generation-recombination current. The substrate current has a high value at low measurement temperatures, high drain voltages, high impurity concentrations of silicon substrates, thin gate-oxide thicknesses and a large drain current. These experimental results were semi-quantitatively explained on the basis of a model in which the substrate current is caused by the first-order impact ionization of the carriers within the pinched-off region. The observed increase of the substrate current is mainly dominated by an increase of the drain current, and the decrease of the substrate current is mainly dominated by a decrease of the impact ionization coefficient.

Superintegrated v-groove isolated bipolar and vmos transistors

Abstract: The invention concerns a semiconductor structure having a compatible mixture of bipolar and unipolar transistors. In that structure a monocrystalline p-type silicon substrate is employed which has its 1-0-0 crystallographic planes at a face on which an n epitaxial layer was grown. The epitaxial layer is divided into electrically isolated parts by V-grooves that extend down through the epitaxial layer and have their apices terminating in the substrate. A thin silicon dioxide film coats the V-grooves and those grooves are filled with polycrystallie silicon. Where it is desired to use the polycrystalline silicon as the insulated gate of a field effect transistor, the polycrystalline silicon is electrically conductive. Bases for bipolar transistors are formed by diffusion of an appropriate impurity into selected areas of the epitaxial layer. The emitters, drains, and sources are formed by diffusion of a different impurity. Each field effect transistor has its drain and source on adjacent parts of the epitaxial layer which are separated by the V-groove in which the gate is situated. The base and emitter of a bipolar transistor may be situated on one isolated part and the collector may be situated on an adjacent part separated by a V-groove having an electrically conductive polycrystalline filler.

Raised source and drain igfet device fabrication

Abstract: Disclosed is an integrated circuit field effect transistor having a source and drain which protrude above the silicon substrate so as to create shallow junctions with the substrate while maintaining a relatively low sheet resistivity in the region. Two self-aligned source and drain fabrication processes are disclosed for the device. The first process yields a polysilicon field shield and the second process yields a field region composed of thermal silicon dioxide.

Integrated circuit device including both N-channel and P-channel insulated gate field effect transistors

Abstract: A complementary integrated circuit device, adapted for fabrication with relatively high circuit density, includes relatively fast transistors with a closed gate geometry. Permanently-off gates surround transistors to isolate them from other transistors.

Noise performance of gallium arsenide field-effect transistors

Abstract: After a brief review of the noise-generating mechanisms intrinsic to the GaAs FET, an enumeration is given of the various parasitic elements associated with the FET which affect the noise performance. These elements include, among others, the gate metallisation and source contact resistances, drain-gate feedback capacitance, and source lead inductance. Numerous graphs are presented to illustrate the effects of these elements and the various design parameters on the noise performance. A comparison is made between the theoretically predicted and the measured noise performance of microwave GaAs FET's. The best state-of-the-art noise performance as reported by various laboratories is illustrated graphically for single-stage and multistage FET amplifiers. Finally, some speculation is attempted in regard to the possible reductions in noise figure to be expected from technological and design improvements of GaAs FET's.

Capless annealing of ion‐implanted GaAs

Abstract: A method is reported for capless annealing of ion‐implanted GaAs which gives electrical activation of Se‐implanted wafers nearly identical to that obtained with sputtered silicon nitride caps. State‐of‐the‐art performance has been realized from Schottky‐gate FET’s fabricated from this material.

Thin film transistor and display panel using the transistor

Abstract: A double gated thin film field effect transistor in which cadmium selenide is the semiconductor material. A thin layer of indium is provided on either side of the cadmium selenide conducting channel and after annealing enhances the transconductance of the device and reduces trapping of charge in the semiconductor. The source and drain contacts of the device are a combination of an indium layer and a copper layer which improve the performance of the device.

Complementary insulated gate field effect transistor structure and process for fabricating the structure

Abstract: A complementary insulated gate field effect transistor structure having complementary p-channel and n-channel devices in the same semiconductor substrate and a process for fabricating the structure incorporate oxide isolation of the active device regions, counterdoping of the p-well with impurities of opposite type to obtain a composite doping profile, reduction of Qss in the isolation oxide, doping of the gate and field oxides with a chlorine species and phosphorus doping of the polycrystalline silicon gates.

Silicon-on-sapphire mesa transistor having doped edges

Abstract: Instabilities in the leakage current and threshold voltage of a field effect transistor on an insulator substrate, at both room temperature and after operation at relatively high temperatures (150° C), are substantially reduced by selectively doping edge regions adjacent the transverse side surfaces of the channel region of the field effect transistor, wherein the breakdown voltage of the channel-to-drain junction is substantially increased Atoms are placed in these edge regions to provide therein a carrier concentration of at least 5 × 10 16 atoms-cm -3 of the opposite conductivity type to that of the source and drain regions The doped edge region extends partly across said channel region and extends fully across the side surface at the end of the source region

Enhancement/depletion mode field effect transistor driver

Abstract: Disclosed is a field effect transistor (FET) driver circuit capable of full supply voltage signal swings and high switching speeds while dissipating relatively little power. The output is obtained from a node between two series connected enhancement mode devices. The first of these series connected enhancement mode devices receives an input signal at its gating electrode, while the second of this pair of series connected devices has its gating electrode capacitively coupled to the output node through a first gatable depletion mode device. The first depletion mode device is in a series electrical path with a second depletion mode device and an enhancement mode device. The second depletion mode device and the enhancement mode device in series therewith receive the same phase of the input signal as the gate of said one series connected output transistor while the first gated depletion mode device is either self-biased or gets a gating input that is out of phase therewith. A depletion mode device in parallel with one of the series connected enhancement mode output devices maintains the output node at a full supply voltage level.

A high power MOSFET with a vertical drain electrode and a meshed gate structure

Abstract: A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.

Isolated semiconductor gate control circuit

Abstract: A circuit for the generation or development of a gating signal for a semiconductor device which is isolated from the circuit of the device itself is comprised of a pulse generating section which feeds pulses to the primary winding of a transformer to thereby induce pulses into the transformer secondary winding. An output section is connected to the secondary winding of the transformer which provides alternately, relatively positive and negative going output signals which serve as the gating signals for the semiconductor device. As provided in the preferred embodiment, the semiconductor device is a field effect transistor and the output section insures that during times in which it is desired to have the transistor conducting, a relatively positive pulse is applied to the gate electrode of the field effect transistor while during periods between pulses, when it is desired to have the transistor non-conducting, there is a sufficiently negative signal applied to the gate electrode so as to maintain the field effect transistor in its nonconducting state.

Method for forming a narrow channel length MOS field effect transistor

Abstract: A method for fabricating an N-channel silicon MOS field effect transistor on a P-type substrate. The structure retains the natural isolation between devices and the consequent higher device density in an integrated circuit structure than conventional double diffused MOS field effect transistor devices. The device is fabricated by using ion implantation to create an N-type surface layer in the channel and then overcompensating this layer to create a P-type region near the source by ion implanting P-type ions into the source junction region. The source to substrate capacitance is considerably less than that of conventional double diffused MOS devices which provides an improved circuit performance.