Showing papers on "Floorplan published in 2017"

Raster-to-Vector: Revisiting Floorplan Transformation

Abstract: This paper addresses the problem of converting a rasterized floorplan image into a vector-graphics representation. Unlike existing approaches that rely on a sequence of lowlevel image processing heuristics, we adopt a learning-based approach. A neural architecture first transforms a rasterized image to a set of junctions that represent low-level geometric and semantic information (e.g., wall corners or door end-points). Integer programming is then formulated to aggregate junctions into a set of simple primitives (e.g., wall lines, door lines, or icon boxes) to produce a vectorized floorplan, while ensuring a topologically and geometrically consistent result. Our algorithm significantly outperforms existing methods and achieves around 90% precision and recall, getting to the range of production-ready performance. The vector representation allows 3D model popup for better indoor scene visualization, direct model manipulation for architectural remodeling, and further computational applications such as data analysis. Our system is efficient: we have converted hundred thousand production-level floorplan images into the vector representation and generated 3D popup models.

Pervasive Floorplan Generation Based on Only Inertial Sensing: Feasibility, Design, and Implementation

Abstract: Mobile crowdsourcing is deemed as a powerful technique to solve traditional problems. But the crowdsourced data from smartphones are generally low quality, which can induce crucial challenges and hurt the applicability of crowdsourcing applications. This paper presents our study to address such challenges in a concrete application, namely, floorplan generation. Existing proposals mostly rely on infrastructural references or accurate data sources, which are restricted in terms of applicability and pervasiveness. Our proposal called SenseWit is motivated by the observation that people’s behavior offers meaningful clues for location inference. The noise, ambiguity, and behavior diversity contained in the crowdsourced data, however, mean non-trivial challenges in generating high-quality floorplans. We propose: 1) a novel concept called Nail to identify featured locations in indoor space and 2) a heuristic pathlet bundling algorithm to progressively discover the internal layouts of a floorplan. We implement SenseWit and conduct real-world experiments in different spaces to demonstrate its efficacy. This paper offers an efficient technique to obtain high-quality structures (either logical or physical) from low-quality data. We believe it can be generalized to other crowdsourcing applications.

Exploiting 2D Floorplan for Building-Scale Panorama RGBD Alignment

Abstract: This paper presents a novel algorithm that utilizes a 2D floorplan to align panorama RGBD scans. While effective panorama RGBD alignment techniques exist, such a system requires extremely dense RGBD image sampling. Our approach can significantly reduce the number of necessary scans with the aid of a floorplan image. We formulate a novel Markov Random Field inference problem as a scan placement over the floorplan, as opposed to the conventional scan-to-scan alignment. The technical contributions lie in multi-modal image correspondence cues (between scans and schematic floorplan) as well as a novel coverage potential avoiding an inherent stacking bias. The proposed approach has been evaluated on five challenging large indoor spaces. To the best of our knowledge, we present the first effective system that utilizes a 2D floorplan image for building-scale 3D pointcloud alignment. The source code and the data are shared with the community to further enhance indoor mapping research.

Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation

Abstract: When dealing with partially reconfigurable designs on field-programmable gate array, floorplanning represents a critical step that highly impacts system’s performance and reconfiguration overhead. However, current vendor design tools still require the floorplan to be manually defined by the designer. Within this paper, we provide a novel floorplanning automation framework, integrated in the Xilinx tool chain, which is based on an explicit enumeration of the possible placements of each region. Moreover, we propose a genetic algorithm (GA), enhanced with a local search strategy, to automate the floorplanning activity on the defined direct problem representation. The proposed approach has been experimentally evaluated with a synthetic benchmark suite and real case studies. We compared the designed solution against both the state-of-the-art algorithms and alternative engines based on the same direct problem representation. Experimental results demonstrated the effectiveness of the proposed direct problem representation and the superiority of the defined GA engine with respect to the other approaches in terms of exploration time and identified solution.

Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System

Abstract: A realistic assessment of optical networks-on-chip (ONoCs) can be performed only in the context of a comprehensive floorplanning strategy for the system as a whole, especially when the 3-D stacking of electronic and optical layers is implemented. This paper fosters layout-aware ONoC design by developing a physical mapping methodology for wavelength-routed ONoC topologies subject to the floorplanning, placement, and routing constraints that arise in a 3-D-stacked environment. As a result, this paper is able to compare the power efficiency and signal-to-noise ratio of ring-based versus filter-based wavelength-routed topologies as determined by their physical design flexibility.

Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits

Abstract: In 3-D integrated circuits (3-D ICs), through silicon via (TSV) is a critical technique to provide vertical connections. However, the yield and reliability challenge of TSV in industry is one of key obstacles to adopt the 3-D ICs technology. Various fault-tolerance structures by using additional spare TSVs (s-TSVs) to repair faulty functional TSVs (f-TSVs) have been proposed in literature for yield and reliability enhancement. However, these structures are formed in standard cell placement stage where all the f-TSVs are already placed. In reality, since the s-TSVs can be only inserted into the whitespace, the quality of the generated repair solution is strongly dependent on the whitespace distribution. In this paper, we propose an efficient TSV planning and repair framework in floorplanning stage, which takes nonuniform TSV distribution and clustered TSV defect-distribution into account. The proposed framework mainly consists of four stages: 1) a whitespace redistribution algorithm that uses a probability-based strategy to make the whitespace distribution more reasonable for the f-TSV planning. Subsequently, a convex-cost flow-based model for f-TSV allocation considering the fault clustering; 2) a top-down globally partitioning combined with a bottom-up locally merging to partition f-TSVs into groups with minimum hardware cost; 3) the min-cost max-flow algorithm for s-TSV allocation with minimum wirelength overhead; and 4) an integer linear programming-based model to form a fault-tolerance structure with minimum multiplexer delay overhead. The experimental results demonstrate that the proposed repair framework can improve the yield with minimum hardware cost and multiplexer delay overhead.

SeDAR - Semantic Detection and Ranging: Humans can localise without LiDAR, can robots?

Abstract: How does a person work out their location using a floorplan? It is probably safe to say that we do not explicitly measure depths to every visible surface and try to match them against different pose estimates in the floorplan. And yet, this is exactly how most robotic scan-matching algorithms operate. Similarly, we do not extrude the 2D geometry present in the floorplan into 3D and try to align it to the real-world. And yet, this is how most vision-based approaches localise. Humans do the exact opposite. Instead of depth, we use high level semantic cues. Instead of extruding the floorplan up into the third dimension, we collapse the 3D world into a 2D representation. Evidence of this is that many of the floorplans we use in everyday life are not accurate, opting instead for high levels of discriminative landmarks. In this work, we use this insight to present a global localisation approach that relies solely on the semantic labels present in the floorplan and extracted from RGB images. While our approach is able to use range measurements if available, we demonstrate that they are unnecessary as we can achieve results comparable to state-of-the-art without them.

Power-Temperature Stability and Safety Analysis for Multiprocessor Systems

Abstract: Modern multiprocessor system-on-chips (SoCs) integrate multiple heterogeneous cores to achieve high energy efficiency. The power consumption of each core contributes to an increase in the temperature across the chip floorplan. In turn, higher temperature increases the leakage power exponentially, and leads to a positive feedback with nonlinear dynamics. This paper presents a power-temperature stability and safety analysis technique for multiprocessor systems. This analysis reveals the conditions under which the power-temperature trajectory converges to a stable fixed point. We also present a simple formula to compute the stable fixed point and maximum thermally-safe power consumption at runtime. Hardware measurements on a state-of-the-art mobile processor show that our analytical formulation can predict the stable fixed point with an average error of 2.6%. Hence, our approach can be used at runtime to ensure thermally safe operation and guard against thermal threats.

TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip

Abstract: Power consumption has become one of the major challenges in current chip design. One effective low power technology, multiple supply voltages (MSVs), has succeeded in 2D network-on-chip (NoC) design. However, few researches considered the MSV in 3D NoC, especially application-specific 3D NoC. In this paper, a complete three-stage synthesis flow for MSV-driven application-specific 3D NoC is proposed, which involves all the issues of layer assignment, voltage level assignment, 3D NoC synthesis, floorplanning, and post-floorplanning adjustment. First, a unified model is presented considering both layer assignment and voltage level assignment, which achieves the best tradeoff between core power and communication power. After that, a 3D NoC synthesis method is proposed to assign network components (NCs) to each layer and generate interlayer connections while a two-stage floorplanning algorithm is used to determine the positions of both cores and NCs. Finally, a novel transitive closure graph-based post-floorplanning repacking algorithm is applied to further reduce the communication power without changing much of the floorplan. Experimental results show that the proposed method is very effective. Compared to traditional 3D NoC, the proposed method can reduce the core power by about 33.6%; compared to MSV-driven 2D NoC, the proposed method can reduce the communication power by about 52.6%.

Semi-automated Signal Surveying Using Smartphones and Floorplans

Abstract: Location fingerprinting locates devices based on pattern matching signal observations to a pre-defined signal map. This paper introduces a technique to enable fast signal map creation given a dedicated surveyor with a smartphone and floorplan. Our technique (PFSurvey) uses accelerometer, gyroscope and magnetometer data to estimate the surveyor's trajectory post-hoc using Simultaneous Localisation and Mapping and particle filtering to incorporate a building floorplan. We demonstrate conventional methods can fail to recover the survey path robustly and determine the room unambiguously. To counter this we use a novel loop closure detection method based on magnetic field signals and propose to incorporate the magnetic loop closures and straight-line constraints into the filtering process to ensure robust trajectory recovery. We show this allows room ambiguities to be resolved. An entire building can be surveyed by the proposed system in minutes rather than days. We evaluate in a large office space and compare to state-of-the-art approaches. We achieve trajectories within 1.1 m of the ground truth 90% of the time. Output signal maps well approximate those built from conventional, laborious manual survey. We also demonstrate that the signal maps built by PFSurvey provide similar or even better positioning performance than the manual signal maps.

Floorplan and placement methodology for improved energy reduction in stacked power-domain design

Abstract: Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which stacks voltage domains in a design, can effectively improve the power delivery efficiency and thus improve battery lifetime. However, such an approach requires balanced current between different domains across multiple operating scenarios. Furthermore, level shifter insertion (together with shifters' delay impacts), along with placement constraints imposed by power domain regions, can incur power and area penalties. To our knowledge, no existing work performs sub-block-level partitioning optimization for stacked-domain designs. In this paper, we present an optimization framework for stacked-domain designs. Based on an initial placement solution, we apply a flow-based partitioning that is aware of multiple operating scenarios, cell placement, and timing-critical paths to partition cells into two power domains with balanced current and minimized number of inserted level shifters. We further propose heuristics to define regions for each power domain so as to minimize placement perturbation, as well as a dynamic programming-based method to minimize the area cost of power domain generation. In an updated floorplan, we perform matching-based optimization to insert level shifters with minimized wirelength penalty. Overall, our method achieves more than ∼10% and 3X battery lifetime improvements in function and sleep modes, respectively.

A memory-based simulated annealing algorithm and a new auxiliary function for the fixed-outline floorplanning with soft blocks

Abstract: A memory-based simulated annealing (MSA) algorithm is proposed for the fixed-outline floorplanning with soft blocks. MSA constructs a memory pool to store some historical best solutions. Moreover, it adopts a real-time monitoring strategy to check whether a solution has been trapped in a local optimum. In case a solution encounters this predicament, it will be replaced by the one from the memory pool, and the current temperature will be regenerated by continuously perturbing the new solution several times. To meet the fixed-outline requirements, a new auxiliary function is formulated based on the geometric structure of the current floorplan, and it is very helpful in driving MSA to search towards potential solution space. Concretely, the area information of all violated blocks is utilized to construct an auxiliary function. Moreover, the excessive area of a violated block can be weighted by three different coefficients, which depend on the relative position of the block and the fixed-outline. Additionally, due to its simple topology and strong applicability, B $$^{\star }$$ -tree representation is employed to perturb a solution in each generation. The efficiency of the proposed method is demonstrated on six GSRC floorplan benchmark examples with various white space and aspect ratios. Two groups of Matlab simulations show that our approach can achieve better floorplanning results and satisfy both the fixed-outline and non-overlapping constraints while optimizing circuit performance.

Dead space reduction of floorplan using simulated annealing algorithm

Abstract: In the VLSI physical design, Floorplanning is very important step as it optimizes the circuit. The goal of floorplanning is to find a floorplan such that no module overlaps with other, optimize the interconnection between the modules, optimize area of the floorplan and minimize the dead space. In this Paper, we use Simulated Annealing (SA) Algorithm to reduce dead space to optimize area and interconnect of floorplanning problem of VLSI design. The results obtained after the application of SA on different benchmark files is compared with the results of application of different algorithms on same benchmark files and the comparison suggests that the SA gives better result. SA is effective and promising in VLSI floorplan design.

Multi-Objective 3D Floorplanning with Integrated Voltage Assignment

Abstract: Voltage assignment is a well-known technique for circuit design, which has been applied successfully to reduce power consumption in classical 2D integrated circuits (ICs). Its usage in the context of 3D ICs has not been fully explored yet although reducing power in 3D designs is of crucial importance, for example, to tackle the ever-present challenge of thermal management. In this article, we investigate the effective and efficient partitioning of 3D designs into multiple voltage domains during the floorplanning step of physical design. In particular, we introduce, implement, and evaluate novel algorithms for effective integration of voltage assignment into the inner floorplanning loops. Our algorithms are compatible not only with the traditional objectives of 2D floorplanning but also with the additional objectives and constraints of 3D designs, including the planning of through-silicon vias (TSVs) and the thermal management of stacked dies. We test our 3D floorplanner extensively on the GSRC benchmarks as well as on an augmented version of the IBM-HB+ benchmarks. The 3D floorplans are shown to achieve effective trade-offs for power and delays throughout different configurations—our results surpass naive low-power and high-performance voltage assignment by 17% and 10%, on average. Finally, we release our 3D floorplanning framework as open-source code.

Scrubbing-Aware Placement for Reliable FPGA Systems

Abstract: Field Programmable Gate Arrays (FPGAs) provide complex embedded blocks to ease the development of high-performance computing systems for diverse area applications, including among others space, avionics and health. Although the rich set of features is ever expanding, there is one significant shortcoming of the SRAM-based FPGAs which concerns system designers for applications demanding high reliability: their vulnerability to Single Event Upsets (SEUs) which can cause system malfunction. In this work, we propose a placement approach to improve system reliability by reducing the execution time of configuration memory scrubbing, which can be used in conjunction with other reliability mechanisms proposed in the literature. The proposed placement approach is based on i) an automated floorplanning process to shape and locate the design region(s) and ii) a modified version of the Simulated Annealing placement algorithm aiming to reduce the scrubbing time. First, we performed a set of experiments with three QUIP benchmarks to demonstrate the efficiency of the proposed approach at different device utilization levels. Moreover, we illustrated its effectiveness for three different fault tolerance schemes, where scrubbing plays a different role in each one: i) a TMR microcontroller combined with scrubbing, ii) a soft processor protected by a low-cost mitigation scheme including scrubbing and checkpointing, iii) a JPEG encoder protected by a prioritized scrubbing scheduling scheme based on module criticality levels. The experimental results showed that the proposed approach improves system reliability in all the above schemes by reducing critical timing parameters, such as mean-time-to-detect and mean-time-to-repair. This reduction leads to a modest or high reliability improvement depending on the role of scrubbing in the adopted fault tolerance (FT) scheme.

Design, development and implementation of a low power and high speed pipeline A/D converter in submicron CMOS technology

Abstract: This research paper focuses on the design, development and implementation of a pipelined analog to digital (A/D) converter of 8 bits with sampling rate of 25 MHz in 350 nm CMOS process technology. The architecture utilizes the digital correction for each stage based on a 1.5 bit per stage structure. A differential switched capacitor circuit consisting of a cascade gm-C op-amp with 200 MHz ft is used for sampling and amplification in each stage. Differential dynamic comparators are used to implement the decision levels required for the 1.5 bit per stage structure. Correction of the pipeline is accomplished by using digital correction circuit consist of D-latches and full adders. Finally, the paper describes the floorplan and layout of design.

A force directed partitioning algorithm for 3D floorplanning

Abstract: Partitioning is very important to 3D IC physical design. Currently, hMetis (most famous partitioning software package) is widely used for partitioning. However, hMetis is for partitioning of hyper graphs. When the method is used for layer assignment of 3D floorplan/placement, some net might be too long. This paper develops a partitioning algorithm for 3D floorplan. The proposed combines a cost-based heuristic and force directed algorithm, which places the nodes considering attractive force and repulsive force, in order to solve the long net problem. We consider both the wire length and the number of TSVs in this work. The second part of the algorithm has two kinds according to the different emphasis. The experimental results demonstrated our algorithms can effectively reduce the wire length and the number of TSV. By comparing the experimental results of two focuses, we can get the differences and strengths of the two algorithms separately.

Computationally efficient standard-cell FEM-based thermal analysis

Abstract: Thermal analysis of integrated circuits (IC) is a high performance computing problem because the nanoscale spatiotemporal features of the problem result in a large discrete problem. In previous works, compact models of ICs were introduced to speed up the modeling process. However, such methods have limited accuracy as they approximate the underlying physics. They are also ill-suited to simulate the thermal characteristics of an IC at the cell-level. The finite element method (FEM) is an appropriate computational technique for providing both fast and accurate thermal analyses. Considering that the number of cells in modern ICs is on the order of millions, thermal analysis at this abstraction level is a formidable task. Consequently, handling the computational meshes and computing thermal profiles of an IC at the cell-level requires substantial computing power. In order to provide accurate cell-level thermal simulations at a lower computational cost, this work introduces advanced techniques that judiciously trade off mesh granularity with simulation accuracy which allows fast analysis of cell-level floorplans. The proposed cell-homogenization techniques start with a flat cell-level floorplan and a related power trace and produce reduced order meshes that accelerate thermal simulations with a negligible loss in accuracy. Results show that the proposed techniques achieve up to a 90% reduction in the number of nodes in the mesh with less than 5% error in the temperature compared to the full scale mesh. The simulation time is also reduced by an order of magnitude.

Automatic indoor building reconstruction from mobile laserscanning data

Abstract: . Indoor reconstruction from point clouds is a hot topic in photogrammetry, computer vision and computer graphics. Reconstructing indoor scene from point clouds is challenging due to complex room floorplan and line-of-sight occlusions. Most of existing methods deal with stationary terrestrial laser scanning point clouds or RGB-D point clouds. In this paper, we propose an automatic method for reconstructing indoor 3D building models from mobile laser scanning point clouds. The method includes 2D floorplan generation, 3D building modeling, door detection and room segmentation. The main idea behind our approach is to separate wall structure into two different types as the inner wall and the outer wall based on the observation of point distribution. Then we utilize a graph cut based optimization method to solve the labeling problem and generate the 2D floorplan based on the optimization result. Subsequently, we leverage an α-shape based method to detect the doors on the 2D projected point clouds and utilize the floorplan to segment the individual room. The experiments show that this door detection method can achieve a recognition rate at 97% and the room segmentation method can attain the correct segmentation results. We also evaluate the reconstruction accuracy on the synthetic data, which indicates the accuracy of our method is comparable to the state-of-the art.

Evaluation of fault attack detection on SRAM-based FPGAs

Abstract: In this paper we present an extended fault injection approach to configuration memory of SRAM-based FPGAs consisting of inter frame many bits upsets to be used as an evaluation tool for attack detection capability and countermeasure effectiveness in security sensitive design modules. The work presented in this paper is twofold. First, we present the concept of a fault detection mechanism for SRAM-based FPGAs based on redundancy of functional modules to be placed evenly spaced over the FPGA floorplan and composing a fault detection mesh. On the following, we present the results of fault injection at the configuration memory of a SRAM-based FPGA used to evaluate the detection capability of different configurations of such detection module. To this, fault injection is done flipping many bits in sequence, locally, mimicking a laser attack. To demonstrate this concept, it was implemented in a Xilinx 7 Series device. The detection module used in the experiments was built around a substitution box (S-box) that is part of the Rijndael symmetric cryptography and the Advanced Encryption Standard (AES).

Photomosaic floor mapping

Abstract: In one embodiment, a method is disclosed for a robot (e.g., cleaning robot) to produce a bird's eye view (planar) map by transforming from a robot camera view and stitching together images tagged by location. The planar map can then be presented on a user interface as a floorplan, showing the location of objects (such as rugs). A camera is mounted in the cleaning robot sufficiently high in the cleaning robot housing to provide an angled view downward at a floor. The camera's field of view is captured as an image, and a portion or segment of that image is cropped. The cropped segment is transformed from the camera perspective to a planar view (before or after cropping), and is combined with other images to form a map of a floorplan.

An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs

Abstract: This paper proposes an integrated optimization framework for task partitioning, scheduling, and floorplanning on partially dynamically reconfigurable FPGAs In the framework, three problems are represented by a partitioned sequence triple (PS, MS, RS), where (PS, MS) is a hybrid nested sequence pair for floorplanning and RS is a reconfiguration sequence for scheduling The floorplan and schedule of tasks can be computed from the sequence triple in O(n^2) time To integrate the exploration of the scheduling and floorplanning design space, a fast perturbation method is elaborated with a simulated annealing-based search engine, where a randomly chosen task is removed from the sequence triple and then inserted back into a proper position selected from all the n^3 possible combinations of partitions, schedule and floorplan The experimental results demonstrate the efficiency and effectiveness of the proposed framework

Semiconductor device including standard cell and electronic design automation method thereof

Abstract: An electronic design automation method configured to automatically design a semiconductor device includes generating a site-row having a unit height based on a standard cell having the unit height, and generating metal routing tracks which begin at an offset point spaced a specific distance from an origin point of the site-row. The unit height is a non-integer multiple of a spacing of metal lines of one of interconnection layers of the semiconductor device. Using this process, a layout of a plurality of standard cells on a plurality of site-rows, and constituting a Floorplan of the semiconductor device, is generated.

Structure discovery techniques for circuit design and process model visualization

Abstract: Graphs are one of the most used abstractions in many knowledge fields because of the easy and flexibility by which graphs can represent relationships between objects. The pervasiveness of graphs in many disciplines means that huge amounts of data are available in graph form, allowing many opportunities for the extraction of useful structure from these graphs in order to produce insight into the data. In this thesis we introduce a series of techniques to resolve well-known challenges in the areas of digital circuit design and process mining. The underlying idea that ties all the approaches together is discovering structures in graphs. We show how many problems of practical importance in these areas can be solved utilizing both common and novel structure mining approaches. In the area of digital circuit design, this thesis proposes automatically discovering frequent, repetitive structures in a circuit netlist in order to improve the quality of physical planning. These structures can be used during floorplanning to produce regular designs, which are known to be highly efficient and economical. At the same time, detecting these repeating structures can exponentially reduce the total design time. The second focus of this thesis is in the area of the visualization of process models. Process mining is a recent area of research which centers on studying the behavior of real-life systems and their interactions with the environment. Complicated process models, however, hamper this goal. By discovering the important structures in these models, we propose a series of methods that can derive visualization-friendly process models with minimal loss in accuracy. In addition, and combining the areas of circuit design and process mining, this thesis opens the area of specification mining in asynchronous circuits. Instead of the usual design flow, which involves synthesizing circuits from specifications, our proposal discovers specifications from implemented circuits. This area allows for many opportunities for verification and re-synthesis of asynchronous circuits. The proposed methods have been tested using real-life benchmarks, and the quality of the results compared to the state-of-the-art.

Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs

Abstract: In this paper, we propose a three-stage reconfigurable topology synthesis approach for Application-Specific NoC (ASNoC) on partially dynamically reconfigurable FPGAs, where the topology is reconfigured dynamically at run-time along with the application’s execution. Firstly, given the scheduling and floorplanning of task modules, an Integral Linear Programming (ILP)-based method is proposed to partition the communication requirements of the application into T time intervals. Secondly, we explore the proper positions of switches in the floorplan for global communications. Finally, considering the reconfiguration costs between adjacent time intervals, the routing path allocation problem is solved for time intervals in an iterative procedure to generate fine-grained dynamically reconfigurable ASNoC topologies for the given application. Experimental results show that, compared to the random partition of communication requirements, the proposed ILP-based method can achieve 12.1% power consumption improvement. And, the reconfigurable ASNoC can achieve 36.3% power consumption improvement when compared with static ASNoCs.