Showing papers on "Gate driver published in 2014"

A step-up switched-capacitor multilevel inverter with self-voltage balancing

Abstract: The objective of this paper is to propose a new inverter topology for a multilevel voltage output. This topology is designed based on a switched capacitor (SC) technique, and the number of output levels is determined by the number of SC cells. Only one dc voltage source is needed, and the problem of capacitor voltage balancing is avoided as well. This structure is not only very simple and easy to be extended to a higher level, but also its gate driver circuits are simplified because the number of active switches is reduced. The operational principle of this inverter and the targeted modulation strategies are presented, and power losses are investigated. Finally, the performance of the proposed multilevel inverter is evaluated with the experimental results of an 11-level prototype inverter.

Active Gate Driver for Crosstalk Suppression of SiC Devices in a Phase-Leg Configuration

Abstract: In a phase-leg configuration, the high-switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (crosstalk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes two gate assist circuits to actively suppress crosstalk on the basis of the intrinsic properties of SiC power devices. One gate assist circuit employs an auxiliary transistor in series with a capacitor to mitigate crosstalk by gate loop impedance reduction. The other gate assist circuit consists of two auxiliary transistors with a diode to actively control the gate voltage for crosstalk elimination. Based on CREE CMF20120D SiC MOSFETs, the experimental results show that both active gate drivers are effective to suppress crosstalk, enabling turn-on switching losses reduction by up to 17%, and negative spurious gate voltage minimization without the penalty of decreasing the switching speed. Furthermore, both gate assist circuits, even without a negative isolated power supply, are more effective in improving the switching behavior of SiC devices in comparison to the conventional gate driver with a -2 V turn-off gate voltage. Accordingly, the proposed active gate assist circuits are simple, efficient, and cost-effective solutions for crosstalk suppression.

A di/dt Feedback-Based Active Gate Driver for Smart Switching and Fast Overcurrent Protection of IGBT Modules

Abstract: This paper presents an active gate driver (AGD) for IGBT modules to improve their overall performance under normal condition as well as fault condition. Specifically, during normal switching transients, a di/dt feedback controlled current source and current sink is introduced together with a push-pull buffer for dynamic gate current control. Compared to a conventional gate drive strategy, the proposed one has the capability of reducing the switching loss, delay time, and Miller plateau duration during turn-on and turn-off transient without sacrificing current and voltage stress. Under overcurrent condition, it provides a fast protection function for IGBT modules based on the evaluation of fault current level through the di/dt feedback signal. Moreover, the AGD features flexible protection modes, which overcomes the interruption of converter operation in the event of momentary short circuits. A step-down converter is built to evaluate the performance of the proposed driving schemes under various conditions, considering variation of turn-on/off gate resistance, current levels, and short-circuit fault types. Experimental results and detailed analysis are presented to verify the feasibility of the proposed approach.

Design and Performance Evaluation of Overcurrent Protection Schemes for Silicon Carbide (SiC) Power MOSFETs

Abstract: Overcurrent protection of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) remains a challenge due to lack of practical knowledge. This paper presents three overcurrent protection methods to improve the reliability and overall cost of SiC MOSFET-based converters. First, a solid-state circuit breaker (SSCB) composed primarily by a Si IGBT and a commercial gate driver IC is connected in series with the dc bus to detect and clear overcurrent faults. Second, the desaturation technique using a sensing diode to detect the drain-source voltage under overcurrent faults is implemented as well. Third, a novel active overcurrent protection scheme through dynamic evaluation of fault current level is proposed. The design considerations and potential issues of the protection methods are described and analyzed in detail. A phase-leg configuration-based step-down converter is built to evaluate the performance of the protection schemes under various conditions, considering variation of fault type, decoupling capacitance, protection circuit parameters, etc. Finally, a comparison is made in terms of fault response time, temperature-dependent characteristics, and applications to help designers select a proper protection method.

Liquid crystal display device and method of driving the same

Abstract: A driving circuit for driving a liquid crystal display device having a plurality of gate lines, data lines and switch elements connected to the gate and data lines includes a data driver for applying a plurality of data signals to the date lines, a gate driver for applying a plurality of gate signals to the gate lines, a timing controller for providing a plurality of control signals to the data and gate drivers, a power supply for generating a power voltage, and a discharging circuit for applying a first signal and a second signal to the gate driver in accordance with the power voltage.

Novel Topologies for Symmetric, Asymmetric, and Cascade Switched-Diode Multilevel Converter With Minimum Number of Power Electronic Components

Abstract: In this paper, novel topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter are proposed, which can produce many levels with minimum number of power electronic switches, gate driver circuits, power diodes, and dc voltage sources. The number of required power electronic switches against required voltage levels is a very important factor in designing of multilevel converter, because switches define the reliability, circuit size, cost, installation area, and control complexity. For asymmetric and cascade converter, new algorithms for determination of dc voltage sources values are presented. To produce maximum number of levels at the output voltage, the proposed cascade topology is optimized for different goals, such as the minimization of the number of power electronic switches, gate driver circuits, power diodes, dc voltage sources, and blocking voltage on switches. Comparison of the results of various multilevel converters will be investigated to reflect the merits of the presented topologies. The operations of the proposed multilevel converters have been analyzed with the experimental and simulation results for different topologies. Verification of the analytical results is done using MATLAB simulation.

Dynamic and static behavior of packaged silicon carbide MOSFETs in paralleled applications

Abstract: There is little work done to study the nuances related to paralleling the higher speed SiC Mosfet devices when compared to Si devices. This paper deals with the parallel operation of packaged silicon carbide (SiC) MOSFETs. The parameters that affect the static and dynamic current sharing behavior of the devices have been studied. We also investigate the sensitivity of those parameters to the junction temperature of the devices. The case temperature difference for paralleled MOSFETs has been experimentally measured on a SEPIC converter for different gate driver resistance and different switching frequency, the results show the current and temperature can be well balanced for the latest generation of SiC MOSFETs with low gate driver resistance.

Liquid crystal display and manufacturing method thereof

Abstract: A liquid crystal display includes a lower panel and an upper panel facing each other. A liquid crystal layer is interposed between the lower panel and the upper panel. An attachment member attaches the lower panel and the upper panel and encloses the liquid crystal layer. A gate driver is integrated on the lower panel. The gate driver generates a gate signal and includes a plurality of stages. A plurality of control signal lines transmit a control signal to the gate driver. A passivation layer is disposed on the gate driver and the plurality of control signal lines. An alignment layer is disposed on the passivation layer and completely covers the gate driver and the plurality of control signal lines. The alignment layer includes a first region and a second region connected to the first region. The second region extends to an edge of the lower panel.

Array substrate and display device

Abstract: An array substrate and a display device are disclosed. The array substrate includes a display area and a gate driver circuit located outside of the display area. The display area is covered with an alignment film, and the gate driver circuit is also covered with the alignment film. With the array substrate, damage, caused by static electricity generated between conductive particles in a sealant and the gate driver circuit, to the gate driver circuit can be effectively reduced.

Liquid crystal display device and method of fabricating the same

Abstract: A Liquid crystal display device and a manufacturing method, as a liquid crystal display device of a gate-in-panel (GIP) type directly embedding a gate driver in an array substrate, is to implement a narrow bezel by reducing a channel size by applying a double gate structure to a GIP circuit part thin film transistor It includes an array substrate divided as a GIP circuit part embedding a gate driver and an active area, a color filter substrate attached to the array substrate, a thin film transistor formed on the array substrate of the active area and composed of a gate electrode, an active layer, and source/drain electrodes, and a GIP circuit part thin film transistor formed on the array substrate of the GIP circuit part and composed of a GIP circuit part gate electrode, a GIP circuit part active layer, and GIP circuit part source/drain electrodes The GIP circuit part gate electrode is composed of a first GIP circuit part gate electrode placed on the bottom of the GIP circuit part active layer and a second GIP circuit part gate electrode placed on the top of the GIP circuit part active layer [Reference numerals] (AA) GIP circuit part; (BB) Active area

A 3600 V/80 A Series--Parallel-Connected Silicon Carbide MOSFETs Module With a Single External Gate Driver

Abstract: In this paper, a new series connection topology is introduced for silicon carbide (SiC) MOSFETs. In the topology, with a single external gate drive, three series-connected SiC MOSFETs are synchronously driven. The operating principle of the proposed topology is analyzed and presented. In order to improve the current capability of the module, parallel connection of two SiC devices are also demonstrated. A 3600 V/80 A series-parallel-connected configuration with three rows in a series and two branches in parallel is constructed with six 1200 V/40 A discrete SiC MOSFETs. Switching behavior of the configuration is completed at 2300 V/78 A. Experimental results verify the validity and feasibility of the proposed topology. Analysis based on experimental results for the circuit switching speed and switching losses is given. Finally, such a series-parallel-connected circuit is integrated in a SiC MOSFETs module, capable of 3600 V/80 A. The switching characteristics of the module are compared to the discrete configuration.

Study of Bonding Wire Failure Effects on External Measurable Signals of IGBT Module

Abstract: The relationship between bonding wire liftoff and terminal voltage in insulated gate bipolar transistor (IGBT) power module is studied. Bonding wire liftoff failure is one of the most dominant limiting factors to the reliability behavior of IGBT power module. In this paper, in order to monitor this type of fault, the effects of the typical degradations are considered. The parasitic inductance and gate equivalent capacitance of IGBT module change due to bonding wire liftoff, which have different impacts on the external characteristics. So, two aspects of IGBT module terminal characteristics are investigated to identify any measurable signature used for monitoring bond wire liftoff failures: 1) gate-emitter voltage during turn-on process and 2) collector-emitter voltage during turn-off process. This paper aims to provide useful information for further development in monitoring the health of IGBT module.

Display device and method of driving the same

Abstract: A display device and a method of driving the same The display device includes a display panel on which a plurality of data lines and a plurality of gate lines intersect each other to form a matrix, with a number of pixels being defined at intersections of the plurality of data lines and the plurality of gate lines A data driver is connected to the plurality of data lines A gate driver is connected to the plurality of gate lines A timing controller controls the display panel to operate in a driving mode that changes depending on image signals

An All-SiC High-Frequency Boost DC–DC Converter Operating at 320 °C Junction Temperature

Abstract: This letter presents the design, prototype development, operation, and testing of an 800 kHz, 1 kW, 800 V output boost dc–dc converter module that integrates SiC MOSFET and SiC Schottky diode die. It is observed that when the device loss is dominated by switching loss, the steady-state junction temperature of SiC MOSFET can reach as high as 320 °C. This is the highest self-heated junction temperature operation of SiC power devices under room temperature ambient reported in the literature. The high-frequency switching characteristics and high-temperature thermal reliability of the assessed converter are evaluated in detail. A solder-molten phenomenon during high junction temperature operation is detected and the die-attachment material is thus improved to enhance the high-temperature thermal reliability of the converter module. This study shows that the high-frequency capability of a gate driver and high-temperature die-attachment technology can be limiting factors preventing SiC power devices from operating at higher junction temperatures.

A compact GaN-based DC-DC converter IC with high-speed gate drivers enabling high efficiencies

Abstract: In this paper, we present a novel compact DC-DC converter IC in which normally-off GaN-GITs (Gate Injection Transistors) and gate drivers are integrated into one chip. The DC-DC converter IC can achieve higher efficiency and smaller chip size by reducing parasitic inductances between switching power devices and gate drivers. The gate driver, having a DCFL (Direct Coupled FET Logic) with a buffer amplifier which is consisted of a GaN-HFET (Hetero-junction FET) and GaN-GITs can operate with higher speed and lower power consumption. The fabricated DC-DC converter IC exhibits a peak efficiency as high as 86.6% at 2MHz for the 12V-1.8V conversion.

Design considerations and development of gate driver for 15 kV SiC IGBT

Abstract: The 15 kV SiC N-IGBT is the state-of-the-art high voltage power semiconductor device developed by Cree. The SiC IGBT is exposed to a peak stress of 10-11 kV in power converter systems, with punch-through turn-on dv/dt over 100 kV/μs and turn-off dv/dt about 35 kV/μs. Such high dv/dt requires ultralow coupling capacitance in the dc-dc isolation stage of the gate driver for maintaining fidelity of the signals on the control-supply ground side. Accelerated aging of the insulation in the isolation stage is another serious concern. In this paper, a simple transformer based isolation with a toroid core is investigated for the above requirements of the 15 kV IGBT. The gate driver prototype has been developed with over 100 kV dc insulation capability, and its inter-winding coupling capacitance has been found to be 3.4 pF and 13 pF at 50 MHz and 100 MHz respectively. The performance of the gate driver prototype has been evaluated up to the above mentioned specification using double-pulse tests on high-side IGBT in a half-bridge configuration. The continuous testing at 5 kHz has been performed till 8 kV, and turn-on dv/dt of 85 kV/μs on a buck-boost converter. The corresponding experimental results are presented. Also, the test methodology of evaluating the gate driver at such high voltage, without a high voltage power supply is discussed. Finally, experimental results validating fidelity of the signals on the control-ground side are provided to show the influence of increased inter-winding coupling capacitance on the performance of the gate driver.

Liquid crystal display device and method for driving the same

Abstract: The present invention relates to a liquid crystal display device and a driving method thereof, which prevents image display error and image degradation due to a common voltage distortion by controlling a display period of image display data according to the change size of the image display data and improves reliability. The liquid crystal display device comprises; a liquid crystal panel which displays an image by including a plurality of pixel areas; a timing controller which detects the change size of image data according to the horizontal line by comparing and analyzing the image data inputted from the outside by the one or more horizontal lines and controls a display period of the image data according to the horizontal line by changing one or more signals between gate and data control signals according to the detected change size; a gate driver which drives gate lines of the liquid crystal panel in response to the gate control signal; and a data driver which drives data lines of the liquid crystal panel in response to the data control signal.

High-Efficiency Bridgeless Flyback Rectifier With Bidirectional Switch and Dual Output Windings

Abstract: This paper proposes and analyzes a new bridgeless flyback power factor correction rectifier for ac-dc power conversion. By eliminating four bridge diodes and adding a few circuit elements, the proposed rectifier reduces the primary side conduction loss and improves efficiency. The addition of the new elements has minimal effect on the circuit simplicity because it does not need any additional gate driver and magnetic elements. The losses in the semiconductor devices of the proposed circuit are analyzed and compared with that of the conventional one, followed by transformer design guideline. Experimental results with the practically implemented prototype prove its higher efficiency than its conventional counterparts.

High-Speed Resonant Gate Driver With Controlled Peak Gate Voltage for Silicon Carbide MOSFETs

Abstract: Parasitic inductance in the gate path of a silicon carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200-V silicon carbide MOSFET gate driver are presented, demonstrating the switching loss of 230 μJ at 800 V and 10 A. This represents a 20% reduction in switching losses in comparison to that of conventional gate drive methods.

An Experimental Evaluation of SiC Switches in Soft-Switching Converters

Abstract: Soft-switching converters equipped with insulated gate bipolar transistors (IGBTs) in silicon (Si) have to be dimensioned with respect to additional losses due to the dynamic conduction losses originating from the conductivity modulation lag. Replacing the IGBTs with emerging silicon carbide (SiC) transistors could reduce not only the dynamic conduction losses but also other loss components of the IGBTs. In the present paper, therefore, several types of SiC transistors are compared to a state-of-the-art 1200-V Si IGBT. First, the conduction losses with sinusoidal current at a fixed amplitude (150 A) are investigated at different frequencies up to 200 kHz. It was found that the SiC transistors showed no signs of dynamic conduction losses in the studied frequency range. Second, the SiC transistors were compared to the Si IGBT in a realistic soft-switching converter test system. Using a calorimetric approach, it was found that all SiC transistors showed loss reductions of more than 50%. In some cases loss reductions of 65% were achieved even if the chip area of the SiC transistor was only 11% of that of the Si IGBT. It was concluded that by increasing the chip area to a third of the Si IGBT, the SiC vertical trench junction field-effect transistor could yield a loss reduction of approximately 90%. The reverse conduction capability of the channel of unipolar devices is also identified to be an important property for loss reductions. A majority of the new SiC devices are challenging from a gate/base driver point-of-view. This aspect must also be taken into consideration when making new designs of soft-switching converters using new SiC transistors.

Gate driver and display device including the same

Abstract: A gate driver includes a plurality of stages connected to each other in a cascade manner, where each of the stages includes an input unit which connects a first input terminal and a first node and includes a first input transistor and a second input transistor, where an output terminal of the first input transistor and an input terminal of the second input transistor are connected to a second node, and the input unit further includes a storage capacitor which connects the first input terminal and the second node.

Physics-Based Device-Level Power Electronic Circuit Hardware Emulation on FPGA

Abstract: Accurate models of power electronic devices are necessary for hardware-in-the-loop (HIL) simulators. This paper proposes a digital hardware emulation of device-level models for the insulated gate bipolar transistor (IGBT) and the power diode on the field programmable gate array (FPGA). The hardware emulation utilizes detailed physics-based nonlinear models for these devices, and features a fully paralleled implementation using an accurate floating-point data representation in VHSIC hardware description language (VHDL) language. A dc-dc buck converter circuit is emulated to validate the hardware IGBT and diode models, and the nonlinear circuit simulation process. The captured oscilloscope results demonstrate high accuracy of the emulator in comparison to the offline simulation of the original system using Saber software.

100 MHz, 20 V, 90% efficient synchronous buck converter with integrated gate driver

Abstract: This paper describes a synchronous buck converter based on a GaN-on-SiC integrated circuit, which includes a halfbridge power stage, as well as a modified active pull-up gate driver stage. The integrated modified active pull-up driver takes advantage of depletion-mode device characteristics to achieve fast switching with low power consumption. Design principles and results are presented for a synchronous buck converter prototype operating at 100 MHz switching frequency, delivering up to 7 W from 20 V input voltage. Measured power-stage efficiency peaks above 91%, and remains above 85% over a wide range of operating conditions. Experimental results show that the converter has the ability to accurately track a 20 MHz bandwidth LTE envelope signal with 83.7% efficiency.

A high temperature silicon carbide MOSFET power module with integrated silicon-on-insulator based gate drive

Abstract: This paper presents a board-level integrated silicon carbide (SiC) mosfet power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200 °C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC mosfet phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225 °C.

A 40 V 10 W 93%-Efficiency Current-Accuracy-Enhanced Dimmable LED Driver With Adaptive Timing Difference Compensation for Solid-State Lighting Applications

Abstract: This paper presents a floating-buck dimmable LED driver for solid-state lighting applications. In the proposed driver, an adaptive timing difference compensation (ATDC) is developed to adaptively adjust the off-time of the low-side power switch to enable the driver to achieve high accuracy of the average LED current over a wide range of input voltages and number of output LED loads, fast settling time, and high operation frequency. The power efficiency benefits from the capabilities of using synchronous rectifier and having no sensing resistor in the power stage. The synchronous rectification under high input supply voltage is enabled by a proposed high-speed and low-power gate driver with pseudo-digital level shifters. Implemented in a 0.35 μm 50 V CMOS process, experimental results show that the proposed LED driver can operate at 1 MHz and achieve peak power efficiency of 93% to support a wide range of series-connected output LEDs from 1 to 10 and a wide input range from 10 to 40 V. The proposed LED driver has only 2.8% current error from the average LED current of 345 mA and settles within 8.5 μs after triggering the dimming condition, improving the settling time by 14 times compared with the state-of-the-art LED drivers.

A wide bandgap silicon carbide (SiC) gate driver for high-temperature and high-voltage applications

Abstract: Limitations of silicon (Si) based power electronic devices can be overcome with Silicon Carbide (SiC) because of its remarkable material properties. SiC is a wide bandgap semiconductor material with larger bandgap, lower leakage currents, higher breakdown electric field, and higher thermal conductivity, which promotes higher switching frequencies for high power applications, higher temperature operation, and results in higher power density devices relative to Si [1]. The proposed work is focused on design of a SiC gate driver to drive a SiC power MOSFET, on a Cree SiC process, with rise/fall times (less than 100 ns) suitable for 500 kHz to 1 MHz switching frequency applications. A process optimized gate driver topology design which is significantly different from generic Si circuit design is proposed. The ultimate goal of the project is to integrate this gate driver into a Toyota Prius plug-in hybrid electric vehicle (PHEV) charger module. The application of this high frequency charger will result in lighter, smaller, cheaper, and a more efficient power electronics system.

Online junction temperature measurement via internal gate resistance during turn-on

Abstract: A new method for junction temperature measurement of power semiconductor switches is presented. The measurement exploits the temperature dependent resistance of the temperature sensitive electrical parameter (TSEP): the internal gate resistance. This dependence can be observed during the normal switching transitions of an IGBT or MOSFET, and as a result the presented method uses the integral of the gate voltage during the turn-on delay. A measurement circuit can be integrated into a gate driver with no modification to converter or gate driver operation and holds significant advantages over other TSEP based measurement methods, primarily being: an absence of any dependence on operating conditions such as load current, and the potential to achieve higher sensitivity (20mV/C or more) than alternative TSEPs.

Novel configuration for multilevel DC-link three-phase five-level inverter

Abstract: A new multilevel DC-link three-phase five-level voltage source inverter topology is introduced here. A multilevel DC- link formed from single DC voltage supply and two cascaded half-bridge (CHB) power cells is connected to 12-switch three- phase bridge in such a way that the proposed inverter produces five levels in the output voltage waveform. Compared to comparable inverters, such as symmetrical CHB and hybrid multilevel inverters, the proposed topology maximises the number of voltage levels and reduces the number of utilised DC voltage supplies, switches, gate driver circuits and installation area. A modified fundamental frequency modulation technique based on determination of switching states of inverter is developed, to generate the appropriate switching gate signals. Furthermore, to validate the proposed topology, a low power prototype inverter has been built. The obtained simulation and experimental results ensure the feasibility of the suggested topology and also the compatibility of the used modulation technique.

Gate driver and display apparatus having the same

Abstract: A driver includes a dummy stage and one or more additional stages coupled to the dummy stage The dummy stage includes a first transistor coupled between an input terminal and an output terminal The first transistor includes two electrodes forming at least a first capacitor to store at least a portion of static electricity received through the input terminal The one or more additional stages output gate signals, which may be received, for example, by a display device