Showing papers on "Ground bounce published in 2013"

Power source multiplexer

Abstract: Circuitry, which includes a first switching transistor element having a first gate, a second switching transistor element having a second gate, a third switching transistor element having a third gate, and a fourth switching transistor element having a fourth gate, is disclosed. The first switching transistor element and the third switching transistor element are coupled in series between a first power source and a first downstream circuit. The second switching transistor element and the fourth switching transistor element are coupled in series between a second power source and the first downstream circuit. A voltage swing at the first gate and a voltage swing at the second gate are both about equal to a first voltage magnitude. A voltage swing at the third gate and a voltage swing at the fourth gate are both about equal to a second voltage magnitude.

Phenomenology of Ground Scattering in a Tropical Forest Through Polarimetric Synthetic Aperture Radar Tomography

Abstract: This paper aims at characterizing the scattering mechanisms occurring at the ground level in a tropical forest illuminated by a P-band synthetic aperture radar (SAR). The analysis is carried out based on the multibaseline, fully polarimetric, data set collected by ONERA over Paracou, French Guyana, in the frame of the European space agency campaign TropiSAR. The favorable baseline distribution of this data set results in the possibility of removing most contributions from the vegetation layer by tomographic techniques, thus allowing the generation of a new fully polarimetric single look complex SAR image relative to scattering contributions from the ground level only. Such a ground layer image is then analyzed by considering the variation of its polarimetric signature with respect to terrain local slope and Radar look angle. Two major conclusions are drawn: 1) double bounce scattering from trunk-ground interactions is observed to be the dominant scattering mechanism at the ground level on flat terrains, whereas it rapidly tends to vanish as the topographic slope increases, and 2) the characteristic parameter that rules trunk-ground scattering is not the tree height, but rather the available free path facing the tree, as a result of the presence of nearby trees, undulating topography, or understory preventing double bounce scattering from taking place whenever the ground bounce occurs too far away from the considered tree. The mean free path length resulting from the analysis of this data-set is found to be L ≅ 7 m. Finally, we discuss how the concept of free path length can be accounted for in simple terms by assuming an equivalent extinction model characterized by a variation along the horizontal dimension.

High threshold voltage p-GaN gate power devices on 200 mm Si

Abstract: In this paper, we present high threshold voltage, low on-resistance, and high speed GaN-HEMT devices using a p-GaN layer in the gate stack. There are three novel features - first, for the first time, p-GaN gate HEMTs were fabricated on a 200-mm GaN on Si substrate using a Au-free fully CMOS-compatible process. Second, good electrical characteristics, including a threshold voltage of higher than 2.8 V, a low gate leakage current, no hysteresis, and fast switching, were obtained by employing a p-GaN and W gate stack. Finally, TO-220 packaged p-GaN gate HEMT devices, which can sustain a gate bias of up to 20 V, were demonstrated. Such properties indicate that our p-GaN HEMT devices are compatible with the conventional gate drivers for Si power devices.

New concept high-voltage IGBT gate driver with self-adjusting active gate control function for SiC-SBD hybrid module

Abstract: We present a new concept in insulated-gate bipolar transistor (IGBT) gate drivers with a blocking voltage up to 3.3kV that have a pulse transformer interface and a function for self-adjusting active gate control. The error-correcting decoder we proposed contributed to the reliability of signal transmission. Moreover, the method of gate control using differentiation of gate voltage could automatically adjust the timing of gate controls against variations in the threshold voltage or collector current without the use of external sensors. These functions were integrated into custom ICs. The new concept high-voltage IGBT gate drivers applied to a 3.3 kV/1200A silicon carbide Schottky barrier diode (SiC-SBD) hybrid-module suppressed ringing in the SiC-SBD and reduced the slew rate by 70%.

Design considerations for stacked Class-E-like mmWave high-speed power DACs in CMOS

Abstract: This work describes design considerations for realizing high power mmWave DACs with high efficiency under modulation based on switching-PA DAC cells. A stacked Class-E-like SOI CMOS power amplifier is turned ON/OFF by means of digital circuitry to sustain high-speed 1-bit ASK (OOK) modulation, while high average efficiency is achieved by means of supply-switching. Factors affecting modulation speed, dynamic power dissipation, impact of digital path delays and supply/ground bounce are discussed and design guidelines are provided. A fully-integrated 47GHz prototype has been fabricated in IBM's 45nm SOI CMOS technology. Measurement results yield a saturated output power of 18.2 dBm with a peak PAE of 15.3% under static (continuous-wave) operation, and high-speed OOK modulation (upto 1Gbps and beyond) is demonstrated with high average efficiency.

Nonvolatile memory device and a method of adjusting a threshold voltage of a ground selection transistor thereof

Abstract: A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device includes providing a first voltage to a gate of a first ground selection transistor in a read operation and providing a second voltage to a gate of a second ground selection transistor in the read operation The nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate

Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation

Abstract: Power supply noise and ground bounce can cause considerable path delay variations. Capturing the worst case power supply noise at a gate level is not a sufficient indicator for measuring the worst case path delay. Furthermore, path delay variations depend on multiple parameters such as input stimuli, cell placement, switching frequency, and available decoupling capacitors. All these variables obscure the rapport between supply noise and path delay and make the selection of stimuli for worst case path delay a difficult task during test pattern generation. In this paper, we utilize power supply noise and ground bounce distribution along with physical design data to generate test patterns for capturing worst case path delay. We propose accurate close-form mathematical models for capturing the effect of power supply noise and ground bounce on path delay. These models are based on modified nodal analysis formulation of power and ground networks, where current waveforms are obtained from levelized simulation and cell library characterization. The proposed test pattern generation flow is a simulated-annealing-based iterative process, which utilizes mathematical models for capturing the impact of supply noise on path delay for a given input pattern. We perform experiments on ITC'99 benchmarks and show that path delay variation can be considerable if test patterns are not properly selected.

Light-emitting device and method for driving the same

Abstract: Provided is a light-emitting device which can prevent appearance of an after-image after power on. Before or after supply of a power voltage applied to a light-emitting element is cut, a potential of a gate electrode of a transistor controlling the supply of the power voltage to the light-emitting element is initialized. Specifically, in the case where the transistor is n-channel type, the potential of the gate electrode is initialized so that a gate voltage is equal to or lower than a threshold voltage. In the case where the transistor is p-channel type, the potential of the gate electrode is initialized so that the gate voltage is equal to or higher than the threshold voltage.

Inverter, nand gate, and nor gate

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Low complexity gate line driver circuitry

Abstract: Gate driver circuitry that controls an array of display elements is described. The gate driver circuitry has gate drivers that apply a control pulse to each of a number of gate lines in sequence, from a previous gate line to a current gate line, during a frame interval in which the array of display elements is filled with pixel values. Each gate driver has a latch stage followed by an output stage. The output stage is coupled to drive a current gate line, and the latch stage is coupled to drive a) a first hold circuit that holds the current gate line at a predetermined voltage, and b) a second hold circuit that holds a previous gate line at a predetermined voltage. Other embodiments are also described and claimed.

Gate drive circuit for transistor

Abstract: In a gate drive circuit, a gate voltage limiting circuit limits a gate voltage equal to or lower than a first limiting voltage in a first period, and limits the gate voltage equal to or lower than a second limiting voltage in a second period. A gate voltage generation circuit generates a drive voltage having a first set value, which is determined to operate the transistor in an active region, in the first period, and generates the drive voltage having a second set value, which is determined based on a gate withstand voltage of the transistor and loss in an on operation of the transistor in a saturated region, in the second period. The first limiting voltage is higher than the first set value by a predetermined value. The second limiting voltage is higher than the second set value by a predetermined value.

A new resonant gate driver with bipolar gate voltage and gate energy recovery

Abstract: This paper presents a new resonant gate driver for voltage driven power devices like MOSFETs and IGBTs. The driver recovers part of the energy that is stored in the gate capacitance and uses it to recharge the capacitance in the next switching cycle. Hence, power consumption of the gate driver is reduced. The paper discusses the circuit operation and the analysis of the circuit. The operation of the circuit is supported by simulated and experimental results. The results show that the gate voltage and current output agree well with the theoretical analysis. Approximately half of the gate drive energy can be recovered during each switching cycle. This allows a smaller gate drive power supply to be used for the gate driver.

Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate

Abstract: A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.

Flash memory cell with capacitive coupling between a metal floating gate and a metal control gate

Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.

Mechanism Study of Gate Leakage Current for AlGaN/GaN High Electron Mobility Transistor Structure Under High Reverse Bias by Thin Surface Barrier Model and Technology Computer Aided Design Simulation

Abstract: Gate leakage current mechanism in GaN high electron mobility transistors (HEMTs) has been studied using a two-dimensional thin surface barrier (TSB) model to represent two unintentional donor thin layers that exit under and outside the gate electrode due to the existence of surface defects. The donor thin layer outside the gate affects the reverse gate current at the high gate voltage above the pinch-off voltage. Higher donor concentration of thin layer outside the gate results in larger ratio of lateral to vertical components of the electric field at the gate edge. On the other hand, the electric field at the center of the gate has only the vertical electric field component. As a result, the two-dimensional effects are only important for the reverse gate current above the pinch-off voltage. We have confirmed in this paper that the simulation results provided by our model correlate very well with the experimental reverse gate current characteristics of the device for a very wide range of reverse gate voltage from 0.1 to 90 V.

Gate sizing in the presence of gate switching activity and input vector control

Abstract: We introduce a novel gate sizing approach that considers both the gate switching activity (SA) and gate input vector control leakage (IVC). We first extract SA using simulation and find promising input vectors. Next, in an iterative framework, we interchangeably conduct gate sizing and refining the IVC. As dictated by the new objective function, our algorithm conducts iterative gate freezing and unlocking with cut-based search for the most beneficial gate sizes under delay constraints. We evaluate our approach on standard benchmarks in 45 nm technology, showing promising improvement, achieving up to 62% (29% avg.) energy savings compared to the traditional objective function.

Voltage compensation type pixel circuit and method for driving the same

Abstract: A voltage compensation pixel circuit includes a driving transistor coupled to the light emitting element between a high potential power line and a low potential power line to drive the light emitting element in response to a predetermined voltage applied to a gate, switching transistor including a first switching transistor being switched in response to a voltage of a first gate signal, a second switching transistor and a third switching transistor being switched in response to a voltage of a third gate signal, and a fourth switching transistor being switched in response to a voltage of a second gate signal, a storage capacitor coupled between a first node and a second node, and a setup transistor coupled between the light emitting element and the driving transistor and operated by the driving transistor. The first node is coupled to the driving transistor. The second node is coupled between the second switching transistor and the fourth switching transistor.

Forward Body Biased Multimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

Abstract: As technology is continuously scaling down leakage current is increasing exponentially. Multi-Threshold CMOS technique is a well known way to reduce leakage current but it gives rise to a new problem i.e. ground bounce noise which reduces the reliability of the circuit and because of this circuit may incorrectly switch to the wrong value or may switch at the wrong time. Ground bouncing noise produced during sleep to active mode transitions is an important challenge in Multi-Threshold CMOS (MTCMOS) circuits. The effectiveness of noise-aware forward body biased multimode MTCMOS circuit techniques to deal with the ground bouncing noise is evaluated in this paper. An additional wait mode is investigated to gradually dump the charge stored on the virtual ground line to the real ground distribution network during the sleep to active mode transitions. The peak amplitude of the ground bouncing noise is reduced by 93.28% and standby leakage current is reduced by 23.94% as compared to standard trimode MTCMOS technique. To evaluate the significance of the proposed multimode Multi-Threshold CMOS technique, the simulation has been performed for 16-bit full adder circuit using BPTM 90nm standard CMOS technology at room temperature with supply voltage of 1V .

Gate driver circuit

Abstract: In High Voltage CMOS technologies the supply voltage is typically higher than the maximum allowed gate voltage. In a switching output stage of amplifiers such class-D amplifiers and DC-DC converters the gates of the power field effect transistors need to be charged quickly. This requires a gate driver that is capable of delivering large currents without exceeding the maximum allowed voltage on the gate of the power field effect transistors.

Apparatus and method for electrical stability compensation

Abstract: Provided is an apparatus and method for electrical stability compensation. The apparatus includes a drive transistor connecting a power supply to a load, a first variable capacitor having a gate and a source, and a switch transistor for controlling a connection between a programming signal source and a gate of the drive transistor. The gate of the first variable capacitor is connected to the gate of the drive transistor. The first variable capacitor is configured to draw a charge from the gate of the drive transistor during a driving phase for the load.

Vertical power transistor with built-in gate buffer

Abstract: A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.

Slew Rate Controlled Transistor Driver

Abstract: A gate driver circuit providing a slew-rate controlled gate control signal while minimizing the stretching of the gate control signal relative to the input control pulse. Control logic effects two threshold voltage levels. When the gate control signal is between the two threshold voltage levels, the slew rate of the gate control signal is controlled such that the gate of the transistor being driven is driven softly. When the gate control signal is less than the first threshold voltage level or greater than the second threshold voltage level, the gate of the transistor being driven is driven hard. In one embodiment, the first and second threshold voltage levels are set such that the on/off threshold of the transistor being driven is between the two threshold voltage levels. Thus the slew rate of the gate control signal is controlled such that the gate of the transistor being driven is driven softly when the transistor being driven is transitioning from off to on, or from on to off, thereby minimizing harmonics. At all other times, the gate control signal rises and falls rapidly so as to minimize the stretching of the gate control signal relative to the input control pulse.

Signal integrity analysis on discontinuous microstrip line

Abstract: In high speed PCB design, microstirp lines were used to control the impedance, however, the discontinuous microstrip line can cause signal integrity problems. In this paper, we use the transmission line theory to study the characteristics of microstrip lines. Research results indicate that the discontinuity such as truncation, gap and size change result in the problems such as radiation, reflection, delay and ground bounce. We change the discontinuities to distributed parameter circuits, analysed the steady-state response and transient response and the phase delay. The transient response cause radiation and voltage jump.

Diode Based Ground Bounce Reduction for 3 bit-Fat-Tree Encoder in Analog to Digital Converter

Abstract: Analog-to-Digital converter is a useful component in the signal processing and communication system. Challenges that the designing of high speed devices and converters in the digital signal processing is facing are low power and low voltage. . Flash ADC is required the efficient design and reduced complexity for high speed and low power devices in signal processing system. This paper describes the ultra high speed ADC design with a fat tree encoder that became highly suitable and accurate. Speed becomes the important part that enhanced by component of 2 guidelines of fat tree encoder. A 3 bit ADC has been designed and simulated in CMOS 45 nm technology with input voltage range of 0 V to 0.7 V. The simulated and analyzed results show low power and a high speed performance for optimised ADC. This paper reports the power gating technique to provide reduction mechanism for suppressing the leakage current effectively during standby mode but it introduce ground noise. We designed a "3" bit flash ADC with power gating technique to reduce leakage current and ground bounce noise in different mode.. This diode based power gating technique provides reduction of leakage current in standby mode, and reduction of ground bounce noise in sleep-to-active mode. The improved power gating technique provides 82% reduction in leakage current, and 73% reduction in ground bounce noise as compared with conventional flash ADC. Fat-tree Encoder with diode based stacking power gating technique has been designed with the help of cadence tool at various supply voltages with 45 nm technology.

A novel ground bounce reduction technique using four step power gating

Abstract: The power gating is a technique to reduce leakage power in standby mode by using Sleep switch. In power gating, the circuit suffers the ground bouncing due to the switching of the Sleep Transistor from standby mode to active mode. In this paper, we have presented a four step power gating technique for further reducing the Ground/Power bouncing. This technique not only controls the bouncing but also controls the wake-up time and transition energy overheads in transition period. To control the wakeup time, pre-boosting and post-boosting current technique is applied by using two MOS transistors, limiting the discharge current and voltage swing in noise limiting stage. Application of proposed technique reduces 73% and 20% bounce noise as compared to conventional power gating and three step power gating techniques respectively. Simulations are carried out using 4-bit Ripple Carry Adder as low Vth logic circuit in Cadence Virtuoso simulation environment and UMC 0.18μm technology.

Diode Based Ground Bounce Noise Reduction for 3-Bit Flash Analog to Digital Converter

Abstract: Flash ADC is an important component for realization of high speed and low power devices in signal processing system .As technology scale down, leakage current becomes the most concerned factor. This paper reports the power gating technique to provide the reduction mechanism for suppressing the leakage current effectively during standby mode but it introduces ground bounce noise. We designed a “3” bit flash ADC with power gating technique to reduce leakage current and ground bounce noise in different mode of operation. This diode based power gating technique provides the reduction of leakage current in standby mode, and reduction of ground bounce noise in sleep-to-active mode. The improved power gating technique provides 82% reduction in leakage current, and 73% reduction in ground bounce noise as compared with conventional flash ADC. Flash ADC with diode based stacking power gating technique has been designed with the help of cadence tool at various supply voltages with 45 nm technology.

Managing signal and power integrity using power transmission lines and alternative signaling schemes

Abstract: Signal and power integrity are crucial for ensuring good performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) becomes a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). Previous works have demonstrated the validity of the Power Transmission Line concept in terms of SSN reduction and power consumption reduction [1-4]. However, these works focused on small systems with just a few bits. This paper shows the effectiveness of the PTL concept on a large scale system with a large number of I/O pins through an FPGA implementation to simulate the memory interface such as DDR3.

Power gating circuit

Abstract: A power gating circuit comprises an output power tube connected between a power supply and a circuit module, a pull-up circuit, a weak current source, a pull-down circuit and a voltage detection circuit, wherein when the output power tube is closed, the pull-up circuit pulls up a grid electrode of the output power tube to the power supply; when the output power tube is opened, the weak current source outputs a weak pull-down current to the grid electrode of the output power tube, and the voltage detection circuit detects the voltage value of the grid electrode of the output power tube; and when the voltage value is smaller than the set threshold value, the pull-down circuit is controlled to forcefully pull down the grid electrode of the output power tube to the ground. The power gating circuit can solve problems of ground bounce and output voltage fluctuation at the moment of opening the circuit, can enable switching of working states of the circuit to be more stable and reliable, can effectively control the opening speed and the opening time of the output power tube, and is applicable to circuits with different requirements.

In-situ relaxation for improved cmos product lifetime

Abstract: Methods and structures for restoring an electrical parameter of a field-effect transistor in an integrated circuit deployed in an end product. A source, a drain, and a gate electrode of a field-effect transistor are coupled with ground. A restoration voltage is applied to a well beneath the field-effect transistor while the source, the drain, and the gate electrode of the field-effect transistor are coupled with ground. The well may be coupled with either a positive supply voltage or ground when a switch is in a first position during normal operation of the integrated circuit and with the restoration voltage when the switch is in a second position during a relaxation operation.

New high performance low power 4 bit full adder with reduce ground bounce noise

Abstract: In this paper, the low power and reduce Ground Bounce noise 4 bit adder has been proposed. Full adder is the most important basic building block of digital circuits employing arithmetic operation. It is therefore necessary to make these systems more efficient to survive with high speed while consuming low power. As the speed of the circuit increases the most important unwanted parameter exhibited by the circuits is ground bounce noise. In this paper, we have proposed a modified 4 bit full adder based on using multi-threshold CMOS technique. Here we use forward body biased multimode (MTCMOS) technique to evaluate standby leakage current, power and ground bounce noise. All the simulation in this paper has been carried out using cadence virtuoso at 45 nm technology at various voltage and temperatures.