Showing papers on "MOSFET published in 1979"

A New Method to Determine Effective MOSFET Channel Length

Abstract: An accurate and convenient method to determine an effective MOSFET channel length is proposed. This method is based on a computer aided evaluation of an intrinsic MOSFET channel resistance without using special test devices. N-channel silicon-gate MOSFETs were fabricated, and the channel length and its range of device to device scatter were evaluated . To define an effective channel, a simple model of the source-drain (S-D) diffusion layer is proposed. This model shows that the expected transition layer resistance between the S-D diffusion layer and the inverted channel layer agrees with the experimental results. The accuracy of this method is also discussed. It is found to be better than 0.1 µm.

1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints

Abstract: An approach is described for determining the hot-electron-limited voltages for silicon MOSFET's of small dimensions. The approach was followed in determining the room-temperature and the 77 K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 µm. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments. For the 1 µm design considered, the channel hot-electron limits are lower than the substrate hot-electron limits. The maximum voltage, V_{DS} = V_{GS} , is 4.75 V at room temperature (25°C) and 3.5 V at 77 K. More details of the voltage limits as well as the approach for determining them are discussed. Examples of circuits designed with these devices to operate within these hot-electron voltage limits are also discussed.

1 µm MOSFET VLSI technology: Part VII—Metal silicide interconnection technology—A future perspective

Abstract: A major limitation of polycrystalline silicon as a gate material for VLSI applications is its limited conductivity which restricts its usefulness as an interconnection level. An alternative approach which combines a doped polycrystalline silicon layer with a high-conductivity metal silicide such as WSi 2 (polycide) is described. Such polycide layers are demonstrated to provide at least an order of magnitude improvement in interconnection resistance relative to polycrystalline silicon while maintaining the reliability of the polycrystalline silicon gate and the ability to form passivating oxide layers under typical polycrystalline silicon processing conditions.

Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis

Abstract: Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's are derived from the combination of analytical consideration and two-dimensional numerical analysis. An approximate analytical solution for the surface potential is used to derive the threshold voltage, in contrast with the charge conservation approach which has been usually taken. It is shown that the surface potential depends exponentially on the distance from the drain, and this causes the threshold voltage to decrease exponentially with decreasing channel length. The analytical dependence of threshold voltage on device dimensions, doping, and operating conditions is verified by accurate two-dimensional calculations, and the accuracy of the model is attained by slight modification. The breakdown voltage of a short-channel n-MOSFET is lowered by a positive feedback effect of excess substrate current. From two-dimensional analysis of this mechanism, a simple expression of the breakdown voltage is derived. Using this model, the scaling down of MOSFET's is discussed. The simple models of threshold and breakdown voltage of short-channel MOSFET's are helpful both for circuit-oriented analysis and process diagnosis where statistical use of the model is often needed.

Thin film MOSFET's fabricated in laser-annealed polycrystalline silicon

Abstract: Both depletion‐ and enhancement‐mode MOSFET’s have been fabricated with the active transistor channels in laser‐annealed polycrystalline‐silicon films. A dose of 3×1012 31P/cm2 was implanted at 100 keV into 0.5‐μm‐thick poly‐silicon films for the depletion‐mode device, and a dose of 3×1011 11B/cm2 was used for the enhancement‐mode device. The transistors fabricated in the poly‐silicon films show electrical characteristics comparable to those of devices in single‐crystal silicon. In the depletion‐mode device, an electron mobility of ∼450 cm2/Vsec was obtained, and approximately 80% of the phosphorus was electrically active. The surface mobility of electrons was about 340 cm2/V sec in the enhancement‐mode device, and a threshold voltage of approximately 2.5 V was obtained.

Characteristics and limitation of scaled-down MOSFET's due to two-dimensional field effect

Abstract: Practical limitations of minimum-size MOS-LSI devices are investigated through measurement of experimental devices. It is assumed that scaled-down MOSFET's are limited by three physical phenomena. These are 1) poor threshold control which is caused by drain electric field, 2) reduced drain breakdown voltage due to lateral bipolar effects, and 3) hot-electron injection into the gate oxide film which yields performance variations during device operation. Experimental models of these phenomena are proposed and the smallest possible MOSFET structure, for a given supply voltage, is considered. It is concluded that the smallest feasible device has a channel length of 0.52 µm and a gate oxide thickness of 9.4 nm when the supply voltage is 1.5 V. Reliable threshold control is most difficult to realize in an MOS-LSI with the smallest devices.

Temperature dependent threshold behavior of depletion mode MOSFETs. Characterization and simulation

Abstract: During the study of depletion mode MOSFET behavior at low temperatures, unusual changes in the threshold characteristics of the devices were observed First, the effectiveness of the donor implantation in producing a negative threshold voltage shift was significantly reduced At the same time the substrate sensitivity was found to be substantially reduced A third observation was the existence of an unusual structure in the subthreshold region of the device at low temperatures Computer simulation is used to explore these observations and to demonstrate that they are caused by impurity freezeout as temperature is reduced The computer simulation program, usable over the temperature range 50–350 K, is discussed, and a threshold definition suitable for numerical analysis of devices with arbitrary channel structures is developed

Subthreshold behavior of uniformly and nonuniformly doped long-channel MOSFET

Abstract: The subthreshold turnoff behavior of the long-channel MOSFET (metal-oxide-semiconductor field-effect transistor) is characterized by the gate bias swing S needed to reduce the subthreshold current one decade. Here a simple formula for S is derived which includes source-to-substrate reverse bias and ion-implanted doping profile effects. For uniformly doped structures it is shown that curves of given S can be constructed on an oxide thickness versus doping level plot, making estimates of S for any choice of these parameters particularly simple. A separate family of curves is needed for each value of source-to-substrate bias V S . Source-to-substrate reverse bias greatly reduces S in devices with large S values, but cannot reduce S to its theoretical minimum value, S_{\min} = (kT/q) ln 10, at reasonable values of V S . It is found that the effect of nonuniform doping is determined mainly by the dose and centroid of the depleted portion of the excess surface doping, provided buried channels do not occur and provided the implant is not primarily located in the inversion layer itself. Higher doses and deeper implants increase S . The maximum value of S for a given implant dose and source-to-substrate reverse bias occurs for that range of implantation which places the implant near the depletion edge. Consequently, the use of implants in small MOSFET's to control threshold punchthrough and parasitic capacitances will cause turnoff degradation.

A parametric study of power MOSFETs

Abstract: The theoretical limitations of V-grooved and double-diffused power MOSFETs are studied using several design parameters as variables. The results are used to gauge the performance of currently available power MOSFETs and to project the capabilities of future devices. With proper design, the channel resistance can be negligible so that the on-state resistance is that of the bulk material (~8.3xl0-9 VdsB 2.5 Ω.cm2) plus the lead resistance. A transmission line effect associated with long resistive gate electrodes could limit the speed of certain devices. Devices with the capability of switching 10 kW per cm2 of chip area and hundred kilowatt per package are theoretically possible over a very wide voltage range. A new structure is proposed that could raise the power capability by an order of magnitude in very high voltage devices.

1 µm MOSFET VLSI technology: Part II—Device designs and characteristics for high-performance logic applications

Abstract: Micrometer-dimension n-channel silicon-gate MOSFET's optimized for high-performance logic applications have been designed and characterized for both room-temperature and liquid-nitrogen-temperature operation. Appropriate choices of design parameters are shown to give proper device thresholds which are reasonably independent of channel length and width. Depletion-type devices are characterized at room temperature for load device use. Logic performance capability is demonstrated by test results on NOR circuits for representative fan-out and loading conditions. Unloaded ring oscillators achieved switching delays down to 240 ps at room temperature and down to 100 ps at liquid nitrogen temperature.

Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations

Abstract: A MOSFET device structure is disclosed where the channel region has formed therein a buried layer of dopant of the same conductivity type as the source and drain, so that the depletion layers for the PN junctions at the upper and lower boundaries thereof intersect in the middle of the implanted region, effectively forming a buried insulator layer between the source and drain. The presence of this layer increases the distance between the mirrored electrostatic charges in the gate and in the bulk of the substrate beneath the MOSFET, thereby reducing the sensitivity of the threshold voltage of the device to variations in the source to substrate voltage.

High-voltage circuit for insulated gate field-effect transistor

Abstract: A high-voltage circuit for insulated gate field-effect transistors (MOSFETs) is provided wherein two MOSFETs are connected in series, the source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the high-voltage circuit, the drain of the second MOSFET being used as a drain terminal of the circuit. First and second resistors are connected in series between the source terminal and the drain terminal, and a biasing voltage supply is connected between the juncture of both the resistors and the gate of the second MOSFET. By virtue of these connections the "on" resistance of the high-voltage circuit is improved due to the effect of the biasing voltage effect in bringing the second MOSFET into an "on" condition.

1 /spl mu/m MOSFET VLSI technology. VII. Metal silicide interconnection technology - A future perspective

Abstract: For pt.VI see ibid., vol.SC14, no.2, p.282 (1979). A major limitation of polycrystalline silicon as a gate material for VLSI applications is its limited conductivity which restricts its usefulness as an interconnection level. An alternative approach which combines a doped polycrystalline silicon layer with a high-conductivity metal silicide such as WSi/SUB 2/ (polycide) is described. Such polycide layers are demonstrated to provide at least an order of magnitude improvement in interconnection resistance relative to polycrystalline silicon while maintaining the reliability of the polycrystalline silicon gate and the ability to form passivating oxide layers under typical polycrystalline silicon processing conditions.

Computer analysis of punch-through in MOSFETs

Abstract: A two-dimensional numerical analysis is made for MOSFETs having short channel lengths. The short channel MOSFET is especially characterized by the existence of the punch-through current which cannot be explained by the one-dimensional MOSFET models. The two-dimensional analysis makes clear the following facts relating about the punch-through mechanism. The punch-through is a condition in which the depletion layers of the source and the drain connect mutually at the deep region in the substrate even in equilibrium. The punch-through current is injected through the saddle point of the intrinsic potential into the drain region by the electric field from the drain, at the low gate voltages.

Simultaneously forming fully implanted DMOS together with enhancement and depletion mode MOSFET devices

Abstract: A semiconductor fabrication process and the resulting structure is disclosed for an FET device with a precisely defined channel length. Two process embodiments are described to make a diffused MOS device which does not require the use of p-type diffusions to obtain 1 micron channel length. Instead, to accurately define such micron-range channel lengths, a lateral etching technique is employed. To obtain well controlled threshold voltages, the channels are ion implanted. Thus the enhancement portion of the diffused MOS device channel is defined by an etching step instead of a diffusion step, thereby producing a channel having a length which is shorter and a threshold voltage which is better controlled than those which have been available in the prior art.

1 /spl mu/m MOSFET VLSI technology. IV. Hot-electron design constraints

Abstract: For pt.III see ibid., vol.SC14, no.2, p.255 (1979). An approach is described for determining the hot-electron-limited voltages for silicon MOSFETs of small dimensions. The approach was followed in determining the room-temperature and the 77K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 /spl mu/m. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments.

1 /spl mu/m MOSFET VLSI technology. II. Device designs and characteristics for high-performance logic applications

Abstract: For pt.I see ibid., vol.SC14, no.2, p.240 (1979). Micrometer-dimension n-channel silicon-gate MOSFETs optimized for high-performance logic applications have been designed and characterized for both room-temperature and liquid-nitrogen-temperature operation. Appropriate choices of design parameters are shown to give proper device thresholds which are reasonably independent of channel length and width. Depletion-type devices are characterized at room temperature for load device use. Logic performance capability is demonstrated by test results on NOR circuits for representative fanout and loading conditions. Unloaded ring oscillators achieved switching delays down to 240 ps at room temperature and down to 100 ps at liquid nitrogen temperature.

Complementary metal-oxide semiconductor

Abstract: A complementary metal-oxide semiconductor being comprised of at least one P channel MOSFET and at least one N channel MOSFET is disclosed. In the above semiconductor, -least one additional doped portion is formed close to at least one of the P and N channel MOSFETs at a small part of the region which is driven by the voltage supply. The additional doped! portion is directly connected to the voltage supply

Insulated gate type field effect transistor

Abstract: PURPOSE:To prevent a negative feedback loop generated when avalanche multiplies and thus prevent the phenomenon of negative resistance generated after drain withstand breakdown by a method wherein the resistance value of a substrate in a high withstand MOSFET is reduced, thus putting the transistor in a structure wherein the drain withstand voltage is determined by the junction voltage between the drain and the substrate. CONSTITUTION:A P type epitaxial layer 1' has the impurity concentration NA at 1.3X10 cm and the thickness at 12mum, and the P type high impurity concentration substrate 1'' has NA at 5X10 cm . A source region 2 and a drain region 3 is 1.5mum deep, and a gate insulation film 6 is 130mum thick. An N type high specific resistance region 5 is formed by ion implantation; the length LR is 13mum, and the amount of ion implantation NDS is 1X10 cm . An N type drain intermediate region is 8mum deep. The dimensions of this element are: 4.3X4.3mm. in chip size, 8mum in channel length, and 18cm in channel width. For assembly, a chip is attached and wired by means of an Al wire of 300mum phi. The breakdown characteristic between the drain and source of this MOSFET does not generate negative resistance phenomenon at all.

Method of making an extremely low current load device for integrated circuit

Abstract: A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.

A quadruply self-aligned MOS (QSA MOS) a new short channel high speed high density MOSFET for VLSI

Abstract: A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limit of conventional scaled down MOS VLSI circuits. This device includes four mutually self-aligned areas: poly Si gate area, shallow source drain area to eliminate short channel effect, deep junction area with high conductance and specific contact area to afford efficient metallic interconnection, thus achieving high speed and high density. Fabrication processes involve undercutting of poly Si gate, anisotropic ion etching of SiO 2 and source drain ion implantation. Experimental results of the device and feasibility of MOS RAM with a density of 1 Mbit/6 × 4 mm2storage area are described.

A calibrated model for the subthreshold operation of a short channel MOSFET including surface states

Abstract: Describes a simple two-dimensional subthreshold model for short channel MOSFET's. The effects of surface state density are also included in the model. A regional charge density approximation was used in the solution of Poisson's equation and an analytical solution of the continuity equation in two dimensions was derived. Excessive computations are avoided in the present model; this was made possible by the use of a valid regional charge approximation. The model was experimentally verified by performing measurements on short channel devices. The model was calibrated from measurements on a long channel device which was present on the same silicon chip. Results are presented for the subthreshold leakage current as a function of substrate bias, polysilicon gate length, diffusion depth and surface state density.

Process statistics of submicron MOSFET's

Abstract: Results of experimental measurements and 2D computer modeling for submicron MOSFET's are presented. Statistical measurements are shown for MOSFET's with masked channel lengths ranging from 10.2 to 1.3 microns. It is shown by means of two-dimensional device analysis that the observed statistics are a result of both the design parameters such as junction profiles and variations in L eff due to process control.

Complementary MOSFET device and method of manufacturing the same

Abstract: A CMOS device comprising an N type semiconductor substrate, a P type well region diffused in the substrate, an n-channel MOS transistor formed in the P type well region, and a p-channel MOS transistor formed in the N type semiconductor substrate, and a method for manufacturing the CMOS device. In case the CMOS device serves as a CMOS inverter, the source region of the p-channel MOS transistor, the semiconductor substrate and the well layer constitute a parasitic PNP type bipolar transistor, and the source region of the n-channel MOS transistor, the well layer and the semiconductor substrate constitute a parasitic NPN type bipolar transistor. The product of the current amplification factor β1 of the PNP type bipolar transistor and the current amplification factor β2 of the NPN type bipolar transistor is smaller than 1.

An MOS field‐effect transistor fabricated on a molecular‐beam epitaxial silicon layer

Abstract: An MOS field‐effect transistor which has a buried channel structure and operates in the depletion mode is first fabricated on a molecular‐beam epitaxial silicon layer. The field‐effect mobility of this MOSFET is comparable to those of the MOSFET’s fabricated on conventional single crystals of silicon.

A discrepancy in the elementary theory of MOSFET modeling

Abstract: The elementary theories of flicker noise in MOSFET’s operating at low drain bias evaluate the spectrum SVeq8f) of the equivalent gate noise emf δVeq under the assumptions of an effective mobility μeff that is independent of the gate voltage Vg and of a carrier number in the channel that varies linearly with the gate voltage We show here that this introduces an error I2d/[g2m(Vg—VT)2] in the calculated results Experiments show that this error can be significant, so that it makes some existing interpretations of SVeq(f) doubtful The error comes about because at a given drain current Id the transconductance gm for large Vg−VT is smaller than the elementary theory predicts This affects most MOSFET modeling at low drain bias

Suppression of anomalous drain current in short channel mosfet.

Abstract: The current voltage characteristics of short channel nMOSFET in the subthreshold region is investigated by two-dimensional numerical analysis. Deep ion implantation of acceptor impurities beneath the channel is found to improve the subthreshold characteristics. Structure optimization for the deeply ion-implanted short channel MOSFET is carried out to obtain low subthreshold current with steep semilogarithmic slope, which are almost comparable with the long channel MOSFET.

Two-dimensional numerical analysis of normally-off type buried channel MOSFET's

Abstract: Two-dimensional numerical analysis of BC(Buried Channel) MOS FETs is performed to investigate short channel behavior of this device. Mechanism of device operation, current path, maximum drain voltage and short channel effects of BC MOS FETs are examined with various device parameters. A design principles of a short channel device are obtained. A test device with a submicron channel length, fabricated according to these principles, is mentioned.

1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography

Abstract: For pt. IV see ibid., vol.SC14, no.2, p.268 (1979). An n-channel single-level polysilicon, 25 nm gate-oxide technology, using electron-beam lithography with a minimum feature size of 1 /spl mu/m, has been implemented for MOSFET logic applications. The six-mask process employs semirecessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques, and reactive ion etching. A description of the process is given, with particular emphasis on topographical considerations. Implementation of a field etchback after source/drain implant to eliminate a low thick-oxide parasitic-device threshold is also discussed.