Showing papers on "MOSFET published in 1983"

Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's

Abstract: The charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI: e.g,, recrystallized Si on SiO 2 ) MOSFET's is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived. The expressions clearly show the dependence of the linear-region channel conductance on the back-gate bias and on the device parameters, including those of the back silicon-insulator interface. The analysis is supported by current-voltage measurements of laser-recrystallized SOI MOSFET's. The results suggest how the back-gate bias may be used to optimize the performance of the SOI MOSFET in particular applications.

Effects of hot-carrier trapping in n- and p-channel MOSFET's

Abstract: Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.

Semi-empirical equations for electron velocity in silicon: Part II—MOS inversion layer

Abstract: We present a simple model of inversion layer and accumulation layer mobilities in Si MOSFET's. The use of an effective normal field and a simple approximation for the temperature dependent quantum mechanically broadened channel layer width Permits the development of a versatile semi-empirical equation. This equation provides good agreement with electron mobility data in the literature as a function of normal electric field, temperature, substrate doping, and fixed charge density. Screening effects have considerable influence in the model. Subthreshold behavior is predicted with reasonable accuracy. The model is also applicable at high tangential fields where mobility is reduced due to hot-carrier effects.

Transconductance degradation in thin-Oxide MOSFET's

Abstract: In this work we investigate the transconductance degradation effect which occurs in thin-oxide FET's due to the finite inversion-layer capacitance and to the decrease of the electron mobility as the electric field increases. Experimental capacitance and charge measurements are performed at room and at liquid-nitrogen temperature on 10-nm oxide FET's, and the data are compared with a classical and a quantum-mechanical model extended to take into account the non-uniform doping profile in the silicon substrate. Accurate mobility determinations are performed accounting for the nonuniform distribution of the mobile charge along the channel, and a mobility expression against the average normal field is incorporated in a generalized Pao-Sah double-integral formula for the FET drain current. Design trade-offs for submicrometer FET's are finally discussed.

Effects of grain boundaries on the channel conductance of SOl MOSFET's

Abstract: A physical model that describes the effects of grain boundaries on the linear-region (strong-inversion) channel conductance of SOI (polysilicon on silicon-dioxide) MOSFET's is developed and supported experimentally. The model predicts an effective turn-on characteristic that occurs beyond the strong-inversion threshold, and henceforth defines the "carrier mobility threshold voltage" and the effective field-effect carrier mobility in the channel, which typically is higher than the actual (intragrain) mobility. These parameters, which are defined by the properties of the grain boundaries, can easily be misinterpreted experimentally as the threshold voltage and the actual carrier mobility.

Silicon-on-insulator bipolar transistors

Abstract: Thin-film lateral n-p-n bipolar transistors (BJT) have been fabricated in moving melt zone recrystallized silicon on a 0.5-µm silicon dioxide substrate thermally grown on bulk silicon. Current-voltage characteristics of devices with different base widths (5 and 10 µm) have been analyzed. The use of a metal gate over oxide covering the base region has allowed the devices to be operated as n-channel MOSFET's as well thus surface effects on device characteristics have been investigated under varying gate-bias voltages. Maximum dc current gain values of 2.5 were achieved with a 5-µm base width and values around 0.5 with a 10-µm base width. Higher gain values were impeded by onset of high-level injection which occurred at low currents because of light base doping of these devices.

Improving the reverse recovery of power mosfet integral diodes by electron irradiation

Abstract: This paper demonstrates that controlled electron irradiation of silicon power MOSFET devices can be used significantly improve the reverse recovery characteristics of their integral reverse conducting diodes without adversely affecting the MOSFET characteristics. By using 3 MeV electron irradiation at room temperature it was found that the reverse recovery charge in the integral diode could be continuously reduced in a well controlled manner from over 500 nC to less than 100 nC without any significant increase in the forward voltage drop of the integral diode under typical operating peak currents. The reverse recovery time was also observed to decrease from 3 microseconds to less than 200 nsec when the radiation dose was increased from 0 to 16 Megarads. The damage produced in gate oxide of the MOSFET due to the electron radiation damage was found to cause an undersirable decrease in the gate threshold voltage. This resulted in excessive channel leakage current flow in the MOSFET at zero gate bias. It was found that this channel leakage current was substantially reduced by annealling the devices at 140°C without influencing the integral diode reverse recovery speed. Thus, the electron irradiation technique was found to be effective in controlling the integral diode reverse recovery characteristics without any degradation of the power MOSFET characteristics.

An As-P(n + -n - )double diffused drain MOSFET for VLSI's

Abstract: An As-P(n+-n-) double diffused drain is characterized as one of the most feasible device structures for VLSI's from the overall viewpoint of device design. This device makes good use of both As, suitable for microfabrication, and P, in realizing a graded junction. The feasibility of this double diffused drain is investigated comparing it with a conventional As drain over the wide range of effective channel length from 0.5 to 5 µm. We have also succeeded in directly measuring hot-hole gate current as low as on the order of 10-15A. This current seems to have an important influence on the hot-carrier effects. On the basis of the experiments and simulations using the two-dimensional process/device analysis programs SUPREM and CADDET, it is shown that this device structure provides remarkable improvements, not only in terms of channel hot-electron effects, but also avalanche hot-carrier effects, which are more responsible for hot-carrier related device degradation due to impact ionization at the drain. In addition, this structure has almost the same short channel effect characteristics, for example threshold-voltage lowering as a conventional MOSFET.

Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on SiO 2

Abstract: A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm2/V.s and drain breakdown voltage exceeding 15 V.

Hot-electron currents in very short channel MOSFET's

Abstract: The behaviors of the hot-electron gate and substrate currents in very short channel devices were studied. For a test device with electrical channel length of 0.14 µm, the hot-electron substrate current can be detected at 0.9-V drain voltage which is lower than the silicon band gap. The gate current can be measured at 2.35-V drain voltage, which is lower than the oxide-silicon energy barrier for electrons. These measurements support the quasi-thermal-equilibrium approximation and suggest that the hot-electron-induced problems cannot be eliminated in future VLSI MOSFET's of arbitrarily short channels by reducing the drain bias below some constant critical energies. An empirical relationship between the effective electron temperature and the field is found to be T e = 9.05 × 10-3E.

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

Abstract: A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BV DC that is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel length L_{eff} µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.

CMOS circuit optimization

Abstract: In this paper, optimization algorithms for CMOS circuits are described, from the propagation delay time viewpoint The propagation delay time for a CMOS in erter is calculated for a step function input A classical model of I–V characteristics for a MOSFET and the worst case Sah model for inter-electrode capacitances of a MOSFET are used for this deduction

Transformer-isolated power MOSFET driver circuit

Abstract: A high power MOSFET switching circuit which has a larger duty cycle is driven from the output winding of a saturable isolation transformer. The output winding is coupled to the gate of the MOSFET power switch through a series connected control MOSFET device having an inherent parallel-connected diode. The gate capacitance is charged through the diode and is discharged through the control MOSFET when it is turned on. The drive circuit is a low impedance circuit with full isolation between input and output terminals.

New grooved-gate MOSFET with drain separated from channel implanted region (DSC)

Abstract: A new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects. Nonimplanted regions between channel implanted and source/drain regions are a unique feature of this device structure. The self-aligned nonimplanted region in the channel is obtained by using silicon dioxide and resist overhangs. These overhangs are fabricated by grooving the silicon substrate. The DSC structure helps reduce the electric field at the drain. Characteristics of experimental devices are presented and compared with those of conventional MOSFET's, from the viewpoint of overall VLSI device design. This device structure is shown to provide remarkable improvements, achieving a 3- or 4-V increase in drain sustaining voltage, as well as a 1- or 2-V increase in the highest applicable voltage as limited by hot-electron injection. In addition, the proposed device can alleviate such short-channel effects as V th lowering, and in particular, diminish narrow-channel effects. The influence of nonimplanted length on breakdown voltage is also clarified using the CADDET, two-dimensional analysis program.

Process for fabrication of stacked, complementary MOS field effect transistor circuits

Abstract: A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.

Analytical model and characterization of small geometry MOSFET's

Abstract: Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.

A simplified model of short-channel MOSFET characteristics in the breakdown mode

Abstract: When a short-channel MOSFET is driven into the avalanche-induced breakdown region, the drain current increases rapidly and usually shows a snapback characteristic. Both the substrate current and the current collected by a nearby reverse-biased p-n junction also increases with increasing drain current in this region of operation. All of these effects are associated with minority-carrier injection from the source junction into the substrate. A model for the drain I-V characteristics is proposed. Also presented is a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation. Experimental results agree well with the models.

A New Short Channel MOSFET with an Atomic-Layer-Doped Impurity-Profile (ALD-MOSFET)

Abstract: A new device structure with an atomic-layer-doped (ALD) impurity profile is proposed to decrease device size and to achieve high speed operation. Device performance is evaluated by computer simulation, and it is clarified that the potential and current flow distributions in MOSFETs with the ALD profile are effectively modulated. Punch-through in ALD MOSFETs is completely suppressed even for Leff=0.2 µm. The minimum channel length, Lmin, restricted by VTH lowering is extended into the submicron range, while the Lmin of conventional structure MOSFETs remains near 1 µm. Furthermore, it is shown that the process margin is sufficient to fabricate ALD MOSFETs by molecular beam epitaxy technology. Thus, it is concluded that the ALD structure is attractive and promising for developing devices with short channels.

Integrated power switching semiconductor devices including igt and mosfet structures

Abstract: Hybrid power switching semiconductor devices advantageously integrate IGT and MOSFET structures. The IGT and MOSFET portions of the overall device include respective gate structures each having an associated gate electrode capacitance, and the hybrid device includes a resistance element connecting the IGT and MOSFET gates. The gate structures preferably comprise polysilicon electrodes, and the resistance element comprises a polysilicon bridge formed at the same time during device fabrication. The overall device has only a single gate terminal, which is connected relatively directly to one of the IGT and MOSFET gates, and indirectly through the resistance element to the other of the IGT and MOSFET gates such that an RC time delay network is defined. Two different types of power switching functions are achieved depending upon whether the overall device gate terminal is connected nearer the IGT gate or the MOSFET gate.

A submicron CMOS megabit level dynamic RAM technology using doped face trench capacitor cell

Abstract: Process technologies for megabit level dynamic RAMs are presented emphasizing submicron channel length MOSFET characteristics and cell size reduction. N-well CMOS composed of 0.5µm n-and 0.9µm p-channel length MOSFETs are used for peripheral circuits which operate at 3V. A Trench capacitor of which face is doped with phosphorus (Doped Face Trench Capacitor) is utilized to increase a cell capacitance and to ground the cell plate. The feasibility of these technologies for megabit level dRAM are verified by a submicron 256K dRAM fabrication.

A long-wavelength optical receiver using a short-channel Si-MOSFET

Abstract: Recent improvements in fine-line technology have resulted in silicon metal oxide semiconductor field-effect transistors (MOSFETs) with channel lengths between 0.2 and 0.8 μm. We have measured the low-frequency noise in these transistors and find it to be smaller than that in comparable GaAs-metal Schottky valve field-effect transistors (MESFETs). Theoretical considerations on the FET noise and experimental results at 45 Mb/s indicate that Si-MOSFETs can compete with GaAs-MESFETs in hybrid photoamplifier circuits. As a natural extension, Si-MOSFETs can also be used for the complete monolithic integration of the receiver circuit with the benefits of reliability and improved performance.

Determination of the spatial variation of interface trapped charge using short-channel MOSFET's

Abstract: Previous measurements of interface trapped charge (ITC) by charge pumping used long-channel metal gate transistors. In this paper charge pumping is extended to short-channel Self-aligned polysilicon gate transistors and used to determine the spatial variation of ITC on wafers. Only the MOSFET gate area and a pulse frequency are required to calculate ITC density from the charge pumping current. In previous work, with long-channel devices, it appears that some investigators used the design dimension of metal gate devices and others used the metallurgical channel length of the transistors to calculate gate area. Two-dimensional simulation of the charge pumping measurement showed that, for a sufficient applied pulse height voltage, the correct area is obtained if the polysilicon gate length and width asmeasured are used. When the process-induced variation of the polysilicon gate length is included in the measurement analysis, no systematic variation of ITC is observed across 5 cm wafers. The charge pumping measurement technique on short-channel MOSFET's can be used to resolve the spatial variation of ITC if the area variations are correctly handled. The measurement of ITC is linear with frequency from 1 kHz to 1 MHz, indicating that the emission time constant of the fast states measured using this method is ≤10-6s. A variation of ITC with channel lengths is also observed. This variation could not be detected using large area devices such as capacitors, but will have important consequences for short-channel MOSFET's.

Structure of stacked, complementary MOS field effect transistor circuits

Abstract: A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.

Effects of grain boundary passivation on the characteristics of p-channel MOSFETs in LPCVD polysilicon

Abstract: p-channel MOSFETs in LPCVD polysilicon have been built. Grain boundary passivation using a plasma of hydrogen has been explored as a means of improving the device performance. Dramatic enhancement of drive current and curtailment of leakage current have been observed. The devices are well suited for application as load elements in CMOS static RAMs.

Modeling total dose effects in narrow-channel devices

Abstract: Exposure of MOSFET's to large doses of ionizing radiation causes bulk oxide charging and an increase in interface state density. The former shifts device operation thresholds. The latter degrades channel mobility g m and increases subthreshold leakage. The degree of damage introduced depends on oxide electric fields. Making gate dimensions smaller complicates modeling a number of ways. Some of these complications are addressed in this paper. Specifically, problems associated with narrowing the width of the device channel are investigated. It is shown that differential charging of the field and gate regions leads to an effective widening of the channel. For typical n-channel MOSFET's used in very-large-scale integrated circuits, this widening may amount to 0.3 µm after a 10-krad:SiO 2 dose of ionizing radiation. A model incorporating channel widening and radiation-induced mobility degradation is proposed.

A model for the relation between substrate and gate currents in n-channel MOSFET's

Abstract: The gate current in n-channel MOSFET's normalized to the source current is expressed as a function of the substrate current normalized to the source current by means of an impact ionization model. The ratio of the electron mean free path for impact ionization to that for optical phonon scattering, which is the most important among the various related device parameters, is determined by indirect measurement of the gate current using stacked-gate MOSFET's. The present model has been applied to interpret the experimental results obtained from samples with a variety of device dimensions. Limitation by the hot-electron emission, which is an important design constraint for submicrometer-gate MOS devices, is studied for single-gate and stacked-gate MOSFET's in comparison with other limiting factors.

Matrix type semiconductor device

Abstract: PURPOSE:To obtain the titled device in which a shift register or the like comprises the sufficient high-speed performance by using an SOI substrate by making a channel direction of MOS type elements the direction of a grain boundary of a semiconductor layer substantially. CONSTITUTION:If a crystallization direction of laser is made parallel to a direction of channels in an SOI substrate, an abnormal diffusion layer 7 of impurity is formed along a grain boundary 6 when a source and drain junction 5 is formed. Accordingly, the source and drain junction 5 tends to be shorten and the possible minimum channel length is about 5mum. For MOSFET10 of a matrix type liquid crystal display device, the predetermind switching function for applying a voltage to a liquid crystal 11 and holding it is necessary. The characteristics of the MOSFET fabricated by SOI technique almost satisfy this function. The switching element used for a liquid crystal display element enables the channel length of 3-5mum or above. Namely, the practical and high-speed matrix type semiconductor device fabricated by SOI technique becomes possible by making a direction of the grain boundary parallel to a direction of the channels.

p-Channel MOSFET's in LPCVD PolySilicon

Abstract: p-channel MOSFET's have been fabricated in LPCVD polysilicon. A 5000-A n+poly acts as the gate electrode on which a 500-A thermal oxide is grown to act as the gate insulator. Then a 1500-A LPCVD polysilicon layer is deposited at 620°C and is subsequently boron doped to form the conductive channel. Devices with channel length as small as 2 µm show well-behaved transistor characteristics. The drive current and leakage current are as suitable for usage as load element in memory applications. At large gate voltages the accumulation hole mobility is 9 cm2/V.s. The drain-to-source breakdown voltage exceeds -20 V.

Metal‐oxide‐semiconductor field‐effect transistors and a ring oscillator fabricated in laser‐recrystallized polycrystalline silicon islands

Abstract: Directions of grain boundaries in laser‐recrystallized polycrystalline silicon (polysilicon) islands are found to be arranged along with the laser scan direction, and are connected to the electrical characteristics of metal‐oxide‐semiconductor field‐effect transistors (MOSFET’s) fabricated in polysilicon islands. When the laser scan is parallel to the channel direction, grain boundaries work as fast‐diffusion paths of arsenic from source and drain into the channel and a decrease of effective channel length of the MOSFET results. But when the laser scan is perpendicular to the channel direction, few grain boundaries are contributed to diffusion paths of arsenic. A maximum electron mobility of 590 cm2/V s approaching that of a single crystalline silicon can be obtained in devices with a channel length of 3 μm, though grain boundaries work as additional potential barriers for carriers. A nine‐stage ring oscillator is fabricated by applying these results. A minimum propagation delay of 38 ns is obtained.

Method of forming a MOSFET with both improved breakdown resistance and less hot-electron effects

Abstract: A field effect transistor has improved punch-through resistance by the implantation of a dose of ions through the center of the active area. The energy of the dose is such that the ion concentration peaks at the depth most susceptible to punch-through. The threshold voltage of the transistor is set by the combination of a lower than normal threshold implant and the tail concentration of the blocking implant.