Showing papers on "Multiplexer published in 2004"

A 4-/spl mu/a quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications

Abstract: This paper describes a dual-mode digitally controlled buck converter IC for cellular phone applications. An architecture employing internal power management is introduced to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology. Special purpose analog and digital interface elements are developed. These include a ring-oscillator-based A/D converter (ring-ADC), which is nearly entirely synthesizable, is robust against switching noise, and has flexible resolution control, and a very low power ring-oscillator-multiplexer-based digital pulse-width modulation (PWM) generation module (ring-MUX DPWM). The chip, which includes an output power stage rated for 400 mA, occupies an active area 2 mm/sup 2/ in 0.25-/spl mu/m CMOS. Very high efficiencies are achieved over a load range of 0.1-400 mA. Measured quiescent current in PFM mode is 4 /spl mu/A.

Electronic educational game set having communicating elements with a radio-frequency tag

Abstract: The invention relates to a game set which comprises communicating elements, in the form of pieces, figurines, cards or dice, each having a radio-frequency tag provided with an individual identification code. A game board comprises a digital processing circuit (15) which is connected to a plurality of antennas (14), arranged such as to form a sensor matrix, for detecting the presence, type and position of the communicating elements. Radio-frequency readers (131 to 13m) are respectively connected to m corresponding input/output terminals of the digital processing circuit (15). Each radio-frequency reader (13) is connected to an associated group of n antennas (141 to 14n), preferably by means of a corresponding multiplexer (161 to 16m). The game board may consist of a removable assembly of basic boards, each comprising a basic digital processing circuit which is connected to the antennas (14) of the corresponding basic board.

A novel multiplexer-based low-power full adder

Abstract: The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster.

Microwave SQUID multiplexer

Abstract: We describe a superconducting quantum interference device (SQUID) multiplexer operated at microwave frequencies. The outputs of multiple SQUIDs are simultaneously modulated at different frequencies and summed into the input of one high electron mobility transistor (HEMT). The large bandwidth and dynamic range provided by HEMT amplifiers should make it possible to frequency-division multiplex a large number of SQUIDs in one output coaxial cable. We measure low SQUID noise (∼0.5μΦ0∕Hz at 4K) and demonstrate the multiplexed readout of two direct current (dc) SQUIDs at different resonant frequencies. In this work, dc SQUIDs are used, but this approach is equally applicable to radio-frequency SQUIDs.

A 4-μA quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications

Abstract: This paper describes a dual-mode digitally controlled buck converter IC for cellular phone applications. An architecture employing internal power management is introduced to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology. Special purpose analog and digital interface elements are developed. These include a ring-oscillator-based A/D converter (ring-ADC), which is nearly entirely synthesizable, is robust against switching noise, and has flexible resolution control, and a very low power ring-oscillator-multiplexer-based digital pulse-width modulation (PWM) generation module (ring-MUX DPWM). The chip, which includes an output power stage rated for 400 mA, occupies an active area 2 mm 2 in 0.25-μm CMOS. Very high efficiencies are achieved over a load range of 0.1-400 mA. Measured quiescent current in PFM mode is 4 μA.

EM-based design of large-scale dielectric-resonator filters and multiplexers by space mapping

Abstract: A novel design methodology for filter and multiplexer design is presented. For the first time, finite-element electromagnetic (EM)-based simulators and space-mapping optimization are combined to produce an accurate design for manifold-coupled output multiplexers with dielectric resonator (DR) loaded raters. Finite-element EM-based simulators are used as a fine model of each multiplexer channel, and a coupling matrix representation is used as a coarse model. Fine details such as tuning screws are included in the fine model. The DR filter and multiplexer design parameters are kept bounded during optimization. The sparsity of the mapping between the design parameters and the coupling elements has been exploited. Our approach has been used to design large-scale output multiplexers and it has significantly reduced the overall tuning time compared to traditional techniques. The technique is illustrated through design of a five-pole DR filter and a ten-channel output multiplexer.

Advanced, self-balancing video multiplexer system

Abstract: An advanced video multiplexer system designed and optimized for next generation on-demand video distribution is described. The system optimizes identifies a multi-program transport stream best able to accommodate new seesions based upon Quality of Service (QoS) and QAM utilization ratios. MPTS channels are rebalanced via re-grouping and transrating as necessary to optimize bandwidth utilization. Multiple video formats are supported via built-in transcoding. The multiplexer manages encryption resources and supports new sessions using previously allocated encryption resources where possible. Sessions can be grouped into encryption channels either by using a single authorization tier per channel policy, or by requiring all clients of the group to be in physically separated service groups. Encryption channels can be released when a channel no longer serves any clients or when one or more other channels that have been assigned the same entitlement can accommodate any remaining clients.

Programmable logic device with time-multiplexed interconnect

Abstract: A PLD includes at least one portion of the programmable interconnect that can be time multiplexed. The time multiplexed interconnect allows signals to be routed on shared interconnect at different times to different destinations, thereby increasing the functionality of the PLD. Multiple sources can use the same interconnect at different times to send signals to their respective destinations. To ensure proper sharing of the interconnect, the sources can include selection devices (such as multiplexers), and the destinations can include capture devices (such as flip-flops), wherein the selection devices and the capture devices are controlled by the same time multiplexing signal. To optimize the time multiplexing interconnect, as much of the same interconnect is shared as possible.

Applications of cascading DSP slices

Abstract: In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

Evaluation of low-leakage design techniques for field programmable gate arrays

Abstract: In this paper we evaluate the trade-offs between various low-leakage design techniques for field programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplexers are widely used in FPGAs for implementing look up tables (LUTs) and connection and routing switches, several low-leakage implementations of pass transistor based multiplexers and routing switches are proposed and their design trade-offs are presented based on transistor-level simulation, physical design, and impact on overall system performance. We find that gate biasing, the use of redundant SRAM cells, and integration of multi-Vt technology are ideal for FPGAs, and they can reduce leakage current by 2X-4X compared to an implementation without any leakage reduction technique. For some of the potential low-leakage design techniques being evaluated in our study, the impact on chip area is very minimal to an increase of 15%-30%.

SiGe heterojunction bipolar transistors and circuits toward terahertz communication applications

Abstract: The relatively less exploited terahertz band possesses great potential for a variety of important applications, including communication applications that would benefit from the enormous bandwidth within the terahertz spectrum. This paper overviews an approach toward terahertz applications based on SiGe heterojunction bipolar transistor (HBT) technology, focusing on broad-band communication applications. The design, characteristics, and reliability of SiGe HBTs exhibiting record f/sub T/ of 375 GHz and associated f/sub max/ of 210 GHz are presented. The impact of device optimization on noise characteristics is described for both low-frequency and broad-band noise. Circuit implementations of SiGe technologies are demonstrated with selected circuit blocks for broad-band communication systems, including a 3.9-ps emitter coupled logic ring oscillator, a 100-GHz frequency divider, 40-GHz voltage-controlled oscillator, and a 70-Gb/s 4:1 multiplexer. With no visible limitation for further enhancement of device speed at hand, the march toward terahertz band with Si-based technology will continue for the foreseeable future.

Lookup table circuit optionally configurable as two or more smaller lookup tables with independent inputs

Abstract: Lookup table (LUT) circuits can optionally be configured as two or more smaller LUTs having independent input signals. A LUT circuit includes a tristate buffer circuit coupled between first and second multiplexer stages. The data input of the tristate buffer circuit is provided as a first output signal from the LUT circuit. The output of the second multiplexer stage provides the second LUT output signal. The tristate buffer circuit can include a tristate buffer with a pullup and a pulldown on the output terminal. To configure the circuit as a single LUT, the buffer is enabled (tristate disabled), and both the pullup and pulldown are turned off. To configure the circuit as two separate LUTs, the buffer is tristated and either the pullup or the pulldown is enabled. Additional multiplexer stages and tristate buffer circuits can be included to enable the division of the circuit into larger numbers of LUTs.

A multiplexer based decoder for flash analog-to-digital converters

Abstract: A decoder for flash analog-to-digital converters with short critical path, regular structure, and small area is presented. The decoder is based on 2:1 multiplexers connected as a tree. Each level of the tree divides the input thermometer scale in two and calculates one of the bits in the binary output. In comparison with the Wallace tree decoder and the folded decoder the length of the critical path is approximately reduced to one third and one half, respectively. The amount of hardware is also reduced, which is likely to translate to a power saving, compared with the Wallace tree decoder and the folded decoder.

Advanced, adaptive video multiplexer system

Abstract: An advanced multiplexer designed and optimized for next generation on-demand video distribution is described. Features and capabilities include auto-discovery, channel-staggering and compatibility with static Virtual Channel Tables (VCTs). The multiplexer system facilitates auto-discovery by inserting identifiers into MPTSs (Multi-Program Transport Streams). These identifiers are echoed back to the multiplexer by the client set-top thereby indicating correspondence between modulators, service groups, and clients. When modulating multiple channels, FEC frames (Forward Error Correction frames) are staggered across channels to reduce correlation and clipping in the IFFT processor.

Systems and methods for testing packaged dies

Abstract: A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

Test set embedding for deterministic BIST using a reconfigurable interconnection network

Abstract: We present a new approach for deterministic built-in self-test (BIST) in which a reconfigurable interconnection network (RIN) is placed between the outputs of a pseudorandom pattern generator and the scan inputs of the circuit under test (CUT). The RIN, which consists only of multiplexer switches, replaces the phase shifter that is typically used in pseudorandom BIST to reduce correlation between the test data bits that are fed into the scan chains. The connections between the linear-feedback shift-register (LFSR) and the scan chains can be dynamically changed (reconfigured) during a test session. In this way, the RIN is used to match the LFSR outputs to the test cubes in a deterministic test set. The control data bits used for reconfiguration ensure that all the deterministic test cubes are embedded in the test patterns applied to the CUT. The proposed approach requires very little hardware overhead, only a modest amount of CPU time, and fewer control bits compared to the storage required for reseeding techniques or for hybrid BIST. Moreover, as a nonintrusive BIST solution, it does not require any circuit redesign and has minimal impact on circuit performance.

Programmable I/O element circuit for high speed logic devices

Abstract: A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer

Structures and methods of implementing a pass gate multiplexer with pseudo-differential input signals

Abstract: Pseudo-differential multiplexer circuits and methods. The circuit input signals are provided to two similar multiplexers, one of which is driven by true signals and one by the complementary input signals. No matter what the values of the circuit input signals, at least one of the two multiplexers always selects a low value. Therefore, at least one of the two multiplexers has the capability of overcoming a value stored in an output circuit (e.g., a latch) coupled to the output terminals of the two multiplexers. Thus, even when neither multiplexer can provide a high signal at the full value of power high VDD, the output circuit provides the correct output value. The invention also encompasses methods of selecting between circuit input signals by utilizing a pseudo-differential multiplexing technique, e.g., utilizing multiplexer circuits similar to those described above.

Register binding and port assignment for multiplexer optimization

Abstract: Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult problem because both register binding and port assignment to reduce total multiplexer connectivity during high-level synthesis are NP-complete problems. In this paper, we first formulate a k-cofamily-based register binding algorithm targeting the multiplexer optimization problem. We then further reduce the multiplexer width through an efficient port assignment algorithm. Experimental results show that we are 44% better overall than the left-edge register binding algorithm on the total usage of multiplexer inputs and 7% better than a bipartite graph-based algorithm. For large designs, we are able to achieve significantly better results consistently. After technology mapping, placement and routing for an FPGA architecture, it shows considerably positive impacts on chip area, delay and power consumption.

Thread-Type Flexible Battery

Abstract: The present invention relates to a ring type optical transmission system having a redundancy structure, which employs Wavelength Division Multiplexing (WDM). The system has a Central Office (CO) for generating optical signals of different wavelengths, multiplexing the optical signals and outputting a multiplexed optical signal, an optical coupler for dividing and transmitting the multiplexed optical signal to different communication lines, and one ring type distribution network formed by the different communication lines through a plurality of optical wavelength add/drop multiplexers, wherein a master optical circulator for outputting optical signals, which are dropped by a corresponding optical wavelength add/drop multiplexer, to a first port and outputting an optical signal, which is received from a second port, to the optical wavelength add/drop multiplexer connected thereto, and an slave optical circulator for outputting optical signals, which are dropped by the optical wavelength add/drop multiplexer, to a first port and outputting an optical signal, which is received from a second port, to the optical wavelength add/drop multiplexer connected thereto, are coupled to each of the optical wavelength add/drop multiplexers.

Programmable circuit optionally configurable as a lookup table or a wide multiplexer

Abstract: Circuits that can be optionally programmed to function as lookup tables (LUTs) or wide multiplexers, and integrated circuits including these programmable circuits. A function select multiplexer is included between each memory cell and the corresponding data input terminal of a first multiplexer. Each function select multiplexer has a first data input terminal coupled to the corresponding memory cell, a second data input terminal coupled to an external input terminal, and a select terminal controlled by a value stored in a function select memory cell. When a first value is stored in the function select memory cell, the programmable circuit functions in the same fashion as a known LUT. When a second value is stored in the function select memory cell, the programmable circuit functions as a wide multiplexer, with the data input values being provided by the external input terminals.

Methods for outlining and filling regions in multi-dimensional arrays

Abstract: A system and method of adding hyperlinked information to a television broadcast. The broadcast material is analyzed and one or more regions within a frame are identified. Additional information can be associated with a region, and can be transmitted in encoded form, using timing information to identify the frame with which the information is associated. The system comprising a video source and an encoder that produces a transport stream in communication with the video source, an annotation source, a data packet stream generator that produces encoded annotation data packets in communication with the annotation source and the encoder, and a multiplexer system in communication with the encoder and the data packet stream generator. The encoder provides timestamp information to the data packet stream generator and the data packet stream generator synchronizes annotation data from the annotation source with a video signal from the video source in response to the timestamp information. The multiplexer generates a digital broadcast signal that includes an augmented transport stream from the transport stream and the encoded data packets. A receiver displays the annotation information associated with the video signal in response to a viewer request on a frame by frame basis. A viewer can respond interactively to the material, including performing commercial transactions, by using a backchannel that is provided for interactive communication.

High-speed lookup table circuits and methods for programmable logic devices

Abstract: A lookup table (LUT) circuit comprises a multiplexer circuit having two modes. In a first mode, the multiplexer circuit functions as a standard multiplexer. In a second mode, the multiplexer circuit selects two or more stored values, where the two or more stored values have the same logical value. Thus, in the second mode the delay through the multiplexer circuit is reduced. In a PLD embodiment, two select terminals of the multiplexer are coupled to two different signal lines. When both signal lines are used, the multiplexer circuit is placed into the first mode. When only one of the signal lines is used, the multiplexer circuit is placed into the second mode, a value on the unused signal line is ignored, and two stored values are provided to the output terminal. Thus, the multiplexer circuit has a reduced path delay when one of the two signal lines is unused.

Layout structure of multiplexer cells

Abstract: A multiplexer cell layout structure is a layout structure of primitive cells where cell arrays composed of P-channel transistors and N-channel transistors are arranged in two upper and lower rows. And, a plurality of transistors of transfer gates are arranged on the upper side and lower side of the cell arrays, an output terminal of the plurality of arranged transistors is connected up and down by Metal wiring across between the upper and lower cell arrays. Thus, a multiplexer cell layout structure which increases wiring tracks of two-layer metal wiring for a one-chip layout held by a 4-input multiplexer inverter can be obtained.

Method and apparatus for the monitoring and control of combustion

Abstract: A sensing apparatus (10) consisting of more than one diode laser (12) having select lasing frequencies, a multiplexer (16) optically coupled to the outputs of the diode lasers with the multiplexer being further optically coupled to a pitch side optical fiber. Multiplexed laser light is transmitted through the pitch side optical fiber to a pitch optic (20) operatively associated with a process chamber (22) which may be a combustion chamber or the boiler of a coal or gas fired power plant. The pitch optic (20) is oriented to project multiplexed laser output through the process chamber. Also operatively oriented with the process chamber is a catch optic (24) in optical communication with the pitch optic to receive the multiplexed laser output projected through the process chamber. The catch optic (24) is optically coupled to an optical fiber which transmits the multiplexed laser output to a demultiplexer (28). The demultiplexer (28) demultiplexes the laser light and optically couples the select lasing frequencies of light to a detector (25) with the detector being sensitive to one of the select lasing frequencies.

VSB transmission system for processing supplemental transmission data

Abstract: A VSB communication system or transmitter for processing supplemental data packets with MPEG-II data packets includes a VSB supplemental data processor and a VSB transmission system. The VSB supplemental data processor includes a Reed-Solomon coder for coding the supplemental data to be transmitted, a null sequence inserter for inserting a null sequence to an interleaved supplemental data for generating a predefined sequence, a header inserter for inserting an MPEG header to the supplemental data having the null sequence inserted therein, a multiplexer for multiplexing an MPEG data coded with the supplemental data having the MPEG header added thereto in a preset multiplexing ratio and units. The output of the multiplexer is provided to an 8T-VSB transmission system for modulating a data field from the multiplexer and transmitting the modulated data field to a VSB reception system.

A 108Gb/s 4:1 multiplexer in 0.13/spl mu/m SiGe-bipolar technology

Abstract: A -3.3-V half-rate clock 4:1 multiplexer implemented in a 210-GHz f/sub T/ 0.13-/spl mu/m SiGe-bipolar technology and operating up to 132 Gb/s is reported. Among many design challenges, the control of on-chop clock distribution was critical to achieve such a high data rate. At 100 Gb/s, the chip operates reliably down to -3.0-V supply voltage and up to 100/spl deg/C chip temperature. The circuit consumes 1.45 W from a -3.3-V supply voltage and exhibits less than 340-fs RMS jitter on the output data.

160-Gb/s OTDM transmission using integrated all-optical MUX/DEMUX with all-channel modulation and demultiplexing

Abstract: This letter provides the first report of 160-Gb/s optical time-division-multiplexed transmission with all-channel independent modulation and all-channel simultaneous demultiplexing. By using a multiplexer and a demultiplexer based on periodically poled lithium niobate and semiconductor optical amplifier hybrid integrated planar lightwave circuits, 160-km transmission is successfully demonstrated.

Analytical synthesis of microwave multiport networks

Abstract: An analytical, exact method for the synthesis of multiport microwave networks formed by coupled resonators is proposed. The method is based on the definition of a novel class of coupling matrix with non-resonant nodes and an arbitrary number of input/output ports. The use of this coupling matrix allows a synthesis procedure analogous to the one used for filters. Some applications of the presented technique are the design of power dividers, multiplexers and diplexers. A synthesis example of a diplexer formed by two box-section filters with one transmission zero at a specified frequency for each one is included.

In-focal-plane SQUID multiplexer

Abstract: Superconducting quantum interference device (SQUID) multiplexers make it possible to build arrays of thousands of microcalorimeters and bolometers based on superconducting transition-edge sensors (TES) with a manageable number of readout channels. Previous to this work, TES arrays were multiplexed by extracting leads from each pixel to multiplexer filter and switching elements outside of the focal plane. As the number of pixels is increased in a close-packed array, it becomes difficult to route the leads to the multiplexer. We report on the development of an in-focal-plane SQUID multiplexer to solve this problem. In this circuit, the filter and switching elements associated with each pixel fit within the pixel area so that signals are multiplexed before being extracted from the focal plane. This in-focal-plane architecture will first be used in the SCUBA-2 instrument at the James Clerk Maxwell Telescope in 2006.