Showing papers on "Operational amplifier published in 2007"

An Energy-Efficient Micropower Neural Recording Amplifier

Abstract: This paper describes an ultralow-power neural recording amplifier. The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date. We describe low-noise design techniques that help the neural amplifier achieve input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage. Since neural amplifiers must include differential input pairs in practice to allow robust rejection of common-mode and power supply noise, our design appears to be near the optimum allowed by theory. The bandwidth of the amplifier can be adjusted for recording either neural spikes or local field potentials (LFPs). When configured for recording neural spikes, the amplifier yielded a midband gain of 40.8 dB and a -3-dB bandwidth from 45 Hz to 5.32 kHz; the amplifier's input-referred noise was measured to be 3.06 muVrms while consuming 7.56 muW of power from a 2.8-V supply corresponding to a noise efficiency factor (NEF) of 2.67 with the theoretical limit being 2.02. When configured for recording LFPs, the amplifier achieved a midband gain of 40.9 dB and a -3-dB bandwidth from 392 mHz to 295 Hz; the input-referred noise was 1.66 muVrms while consuming 2.08 muW from a 2.8-V supply corresponding to an NEF of 3.21. The amplifier was fabricated in AMI's 0.5-mum CMOS process and occupies 0.16 mm2 of chip area. We obtained successful recordings of action potentials from the robust nucleus of the arcopallium (RA) of an anesthesized zebra finch brain with the amplifier. Our experimental measurements of the amplifier's performance including its noise were in good accord with theory and circuit simulations.

500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC

Abstract: A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. Six time-interleaved channels are used, sharing a single clock operating at the composite sampling rate. Each channel has a split capacitor array that reduces switching energy, increases speed, and has similar INL and decreased DNL, as compared to a conventional binary-weighted array. A variable delay line adjusts the instant of latch strobing to reduce preamplifier currents. The ADC achieves Nyquist performance, with an SNDR of 27.8 and 26.1 dB for 3.3and 239 MHz inputs, respectively. The total active area is 0.9mm2, and the ADC consumes 6 mW from a 1.2-V supply

500-MS/s 5-bit ADC in 65-nm COMS with split capacitor array DAC

Abstract: A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. Six time-interleaved channels are used, sharing a single clock operating at the composite sampling rate. Each channel has a split capacitor array that reduces switching energy, increases speed, and has similar INL and decreased DNL, as compared to a conventional binary-weighted array. A variable delay line adjusts the instant of latch strobing to reduce preamplifier currents. The ADC achieves Nyquist performance, with an SNDR of 27.8 and 26.1 dB for 3.3 and 239 MHz inputs, respectively. The total active area is 0.9 mm 2 , and the ADC consumes 6 mW from a 1.2-V supply.

An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing

Abstract: An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier (OTA) with rail-to-rail input/output swing is presented The topology is based on combining bulk-driven differential pair and dc level shifters, with the transistors work in weak inversion The improved Miller OTA has been successfully verified in a standard 035-mum CMOS process Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW

1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage

Abstract: This paper introduces a CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments. The approach is based on a bulk-driven input stage with extended input common-mode voltage range, in which the effective input transconductance is enhanced by means of a partial positive feedback loop. As a result, a gain and gain-bandwidth product performance similar to that of an amplifier using a gate-driven approach is obtained. Output rail-to-rail operation is achieved by means of a push-pull stage, which is biased in class-AB by using a static feedback loop, thus avoiding frequency limitations inherent in dynamic-feedback tuning schemes. The proposed two-stage operational amplifier was designed to operate with a 1-V supply, and a test chip prototype was fabricated in 0.35-mum standard CMOS technology. The experimental performance features an open-loop DC gain higher than 76 dB and a closed-loop unity-gain bandwidth above 8 MHz when a 1-MOmegapar17-pF load is connected to the amplifier output.

Advances in Reversed Nested Miller Compensation

Abstract: The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RN-MCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included.

A Low-Noise Preamplifier with Adjustable Gain and Bandwidth for Biopotential Recording Applications

Abstract: We have developed a fully differential low-power low-noise preamplifier with multiple adjustable parameters for biopotential and neural recording applications. Common mode feedback has been utilized to guarantee the amplifier functionality by forcing the output DC level to a desired voltage. A switch is added to the output to achieve fast settling time in case the amplifier is saturated. The amplifier has been implemented in the AMI 1.5-mum 2M2P standard CMOS process and occupies 0.201 mm2 on chip. The amplifier current consumption is 8 muA at plusmn1.7 V supply, with two measured AC gains of 39.3 dB and 45.6 dB. The low cutoff frequency is 4-bit programmable from 0.015 Hz to 700 Hz. The high cutoff frequency can be adjusted from 120 Hz to 12 kHz at negligible load and 40 Hz to 4 kHz with a 2 pF active probe loading. The measured input referred noise is 3.6 muV over 20 Hz ~ 10 kHz. The amplifier also provides rail-to-rail input DC range, maximum input offset of 0.7 mV, common mode tuning range of plusmn600 mV, and output swing of plusmn0.9 V with minimum distortion.

A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC

Abstract: Zero-crossing-based circuits (ZCBC) are introduced as a generalization of comparator-based switched-capacitor circuits (CBSC) To demonstrate this concept, an 8-bit, 200 MS/s, pipelined ADC is implemented in a 018 CMOS technology A dynamic zero-crossing detector and current source replace the functionality of an opamp to realize a precision charge transfer Furthermore, current source splitting improves linearity at high speeds and bit decision flip-flops replace traditional bit decision comparators for increased speed The complete ADC draws no static current and consumes 85 mW of power The corresponding FOM is 038 pJ/step at 100 MS/s and 051 pJ/step at 200 MS/s

Chopper-stabilized instrumentation amplifier for impedance measurement

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Sense amplifier circuit having current mirror architecture

Abstract: A sense amplifier circuit for use in a semiconductor memory device has complemented logic states at opposite sides of the latch circuit in the sense amplifier circuit determinate all the time in operation. The sense amplifier circuit takes advantage of a current mirror circuit for ascending or descending a voltage level at the gate of a transistor by charge accumulation or charge dissipation, which turns on or off the transistor so as to control the logic states at opposite sides of the latch circuit in the sense amplifier circuit.

A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC

Abstract: A 0.5-V third-order one-bit fully-differential continuous-time DeltaSigma modulator is presented. The presented modulator architecture uses true low-voltage design techniques, and does not require internal voltage boosting or low-threshold devices. A return-to-open architecture that enables the ultra-low-voltage realization of return-to-zero signaling for the feedback DAC is proposed. The ultra-low-voltage operation is further enabled by a body-input gate-clocked comparator, and body-input operational transconductance amplifiers for the active-RC loop filter. Fabricated on a 0.18-mum CMOS process, the modulator achieves a peak SNDR of 74 dB in a 25 kHz bandwidth, and occupies an area of 0.6 mm2; the modulator core consumes 300 muW.

Chopper-stabilized instrumentation amplifier

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Electronic Circuits: Handbook for Design and Application

Abstract: Device Models and Basic Circuits.- Diode.- Bipolar Transistor.- Field Effect Transistor.- Amplifiers.- Operational Amplifiers.- Latching Circuits.- Logic Families.- Combinatorial Circuits.- Sequential Logic Systems.- Semiconductor Memories.- General Applications.- Operational Amplifier Applications.- Controlled Sources and Impedance Converters.- Active Filters.- Signal Generators.- Power Amplifiers.- Power Supplies.- Analog Switches and Sample-and-Hold Circuits.- Digital-Analog and Analog-Digital Converters.- Digital Filters.- Measurement Circuits.- Sensors and Measurement Systems.- Electronic Controllers.- Optoelectronic Components.- Communication Circuits.- Basics.- Transmitters and Receivers.- Passive Components.- High-Frequency Amplifiers.- Mixer.

A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling

Abstract: The residue amplifiers in high-speed pipelined analog-to-digital converters (ADCs) typically determine the converter's overall speed and power performance. We propose a mixed-signal technique that exploits incomplete settling to achieve low power residue amplification. In the first stage of a 12-bit, 75-MS/s proof-of-concept prototype, the employed open-loop residue amplifier dissipates only 2.9 mW from a 3-V supply, achieving >60% amplifier power reduction over a previously reported open-loop residue amplifier implementation and achieving >90% amplifier power reduction over a conventional opamp implementation. Test results show that the converter's maximum signal-to-noise-and-distortion ratio (SNDR) is 65.6 dB. The measured integral and differential nonlinearity are 0.95 LSB and 0.64 LSB, respectively. The experimental chip occupies 7.9 mm2 and consumes 273 mW in a 0.35-mum double-poly, quadruple-metal CMOS process

A 2 W CMOS Hybrid Switching Amplitude Modulator for EDGE Polar Transmitters

Abstract: This paper presents a hybrid switching amplitude modulator for class-E2 EDGE polar transmitters. To achieve both high efficiency and high speed, it consists of a wideband buffered linear amplifier as a voltage source and a PWM switching amplifier with a 2 MHz switching frequency as a dependent current source. The linear amplifier with a novel class-AB topology has a high current-driving capability of approximately 300 mA with a bandwidth wider than 10 MHz. It can also operate on four quadrants with very low output impedance of about 200 at the switching frequency attenuating the output ripple voltage to less than 12 . A feedforward path, a PWM control, and a third-order ripple filter are used to reduce the current burden of the linear amplifier. The output voltage of the hybrid modulator ranges from 0.4 to 3 V for a 3.5 V supply. It can drive an RF power amplifier with an equivalent impedance of 4 up to a maximum output power of 2.25 W with a maximum efficiency of 88.3%. The chip has been fabricated in a 0.35 m CMOS process and occupies an area of 4.7 .

Notch filter for ripple reduction in chopper stabilized amplifiers

Abstract: A chopper-stabilized amplifier receiving an input signal includes a first operational transconductance amplifier (2) having an input chopper and an output chopper for chopping an output signal produced by the first operational transconductance amplifier. A switched capacitor notch filter (15) will filter the chopped output signal by operating synchronously with the chopping frequency of output chopper to filter ripple voltages that otherwise would be produced by the output chopper. In one embodiment a second operational transconductance amplifier amplifies the notch filter output. The input signal is fed forward, summed with the output of the second operational transconductance amplifier, and applied to the input of a fourth operational transconductance amplifier. Ripple noise and offset are substantially reduced.

Microelectronics : circuit analysis and design

Abstract: Microelectronics: Circuit Analysis and Design Prologue I: Prologue to Electronics Brief History Passive and Active Devices Electronic Circuits Discrete and Integrated Circuits Analog and Digital Signals Notation Summary Part I: Semiconductor Devices and Basic Applications Chapter 1: Semiconductor Materials and Diodes 1.0 Preview 1.1 Semiconductor Materials and Properties 1.2 The pn Junction 1.3 Diode Circuits: DC Analysis and Models 1.4 Diode Circuits: AC Equivalent Circuit 1.5 Other Diode Types 1.6 Design Application 1.7 Summary Problems Chapter 2: Diode Circuits 2.0 Preview 2.1 Rectifier Circuits 2.2 Zener Diode Circuits 2.3 Clipper and Clamper Circuits 2.4 Multiple Diode Circuits 2.5 Photodiode and LED Circuits 2.6 Summary Problems Chapter 3: The Field-Effect Transistor 3.0 Preview 3.1 Basic Bipolar Junction Transistor 3.2 DC Analysis of Transistor Circuits 3.3 Basic Transistor Applications 3.4 Bipolar Transistor Biasing 3.5 Multistage Circuits 3.6 Design Application 3.7 Summary Problems Chapter 4: Basic FET Amplifiers 4.0 Preview 4.1 Analog Signals and Linear Amplifiers 4.2 The Bipolar Linear Amplifier 4.3 Basic Transistor Amplifier Configurations 4.4 Common-Emitter Amplifiers 4.5 AC Load Line Analysis 4.6 Common-Collector (Emitter-Follower) Amplifier 4.7 Common-Base Amplifier 4.8 The Three Basic Amplifiers: Summary and Comparison 4.9 Multistage Amplifiers 4.10 Power Considerations 4.11 Design Application 4.12 Summary Problems Chapter 5: Bipolar Junction Transistor 5.0 Preview 5.1 MOS Field-Effect Transistor 5.2 MOSFET DC Circuit Analysis 5.3 Basic MOSFET Applications: Switch, Digital Logic Gate, and Amplifier 5.4 Constant Current Biasing 5.5 Multistage MOSFET Circuits 5.6 Junction Field-Effect Transistors 5.7 Design Application 5.8 Summary Problems Chapter 6: Basic BJT Amplifiers 6.0 Preview 6.1 The MOSFET Amplifier 6.2 Basic Transistor Amplifier Configurations 6.3 The Common-Source Amplifier 6.4 The Source-Follower Amplifier 6.5 The Common-Gate Amplifier 6.6 The Three Basic Amplifier Configurations: Summary and Comparison 6.7 Single-Stage Integrated Circuit MOSFET Amplifiers 6.8 Multistage Amplifiers 6.9 Basic JFET Amplifiers 6.10 Summary Problems Chapter 7: Frequency Response 7.0 Preview 7.1 Amplifier Frequency Response 7.2 System Transfer Functions 7.3 Frequency Response: Transistor Amplifiers with Circuit Capacitors 7.4 Frequency Response: Bipolar Transistor 7.5 Frequency Response: The FET 7.6 High-Frequency Response Transistor Circuits 7.7 Summary Problems Chapter 8: Output Stages and Power Amplifiers 8.0 Preview 8.1 Power Amplifiers 8.2 Power Transistors 8.3 Classes of Amplifiers 8.4 Class-A Power Amplifier 8.5 Class-AB Push-Pull Complementary Output Stages 8.6 Summary Problems Prologue II: Prologue to Electronic Design Preview Design Approach System Design Electronic Design Conclusion Part II: Analog Electronics Chapter 9: Ideal Operational Amplifiers and Op-Amp Circuits 9.0 Preview 9.1 The Operational Amplifier 9.2 Inverting Amplifier 9.3 Summing Amplifier 9.4 Noninverting Amplifier 9.5 Op-Amp Applications 9.6 Operational Transconductance Amplifiers 9.7 Op-Amp Circuit Design 9.8 Design Application 9.9 Summary Problems Chapter 10: Integrated Circuit Biasing and Active Loads 10.0 Preview 10.1 Bipolar Transistor Current Sources 10.2 FET Current Sources 10.3 Circuits and Active Loads 10.4 Small-Signal Analysis: Active Load Circuits 10.5 Summary Problems Chapter 11: Differential and Multistage Amplifiers 11.0 Preview 11.1 The Differential Amplifier 11.2 Basic BJT Differential Pair 11.3 Basic FET Differential Pair 11.4 Differential Amplifier with Active Load 11.5 BiCMOS Circuits 11.6 Gain Stage and Simple Output Stage 11.7 Simplified BJT Operational Amplifier Stage 11.8 Diff-Amp Frequency Response 11.9 Summary Problems Chapter 12: Feedback and Stability 12.0 Preview 12.1 Introduction to Feedback 12.2 Basic BJT Differential Pair 12.3 Basic FET Differential Pair 12.4 Voltage (Series-Shunt) Amplifier 12.5 Current (Shunt-Series) Amplifier 12.6 Transconductance (Series-Series) Amplifier 12.7 Transresistance (Shunt-Shunt) Amplifier 12.8 Loop Gain 12.9 Stability of the Feedback Circuit 12.10 Frequency Compensation 12.11 Summary Problems Chapter 13: Operational Amplifier Circuits 13.0 Preview 13.1 General Op-Amp Design 13.2 A Bipolar Operational Amplifier Circuit 13.3 CMOS Operational Amplifier Circuits 13.4 BiCMOS Operational Amplifier Circuits 13.5 JFET Operational Amplifier Circuits 13.6 Summary Problems Chapter 14: Nonideal Effects in Operational Amplifier Circuits 14.0 Preview 14.1 Practical Op-Amp Parameters 14.2 Finite Open-Loop Gain 14.3 Frequency Response 14.4 Offset Voltage 14.5 Input Bias Current 14.6 Additional Nonideal Effects 14.7 Summary Problems Chapter 15: Applications and Design of Integrated Circuits 15.0 Preview 15.1 Active Filters 15.2 Oscillators 15.3 Schmitt Trigger Circuits 15.4 Nonsinusoidal Oscillators and Timing Circuits 15.5 Integrated Circuit Power Amplifiers 15.6 Voltage Regulators 15.7 Summary Problems Prologue III: Prologue to Digital Electronics Introduction Logic Functions and Logic Gates Logic Levels Noise Margin Propagation Delay Times and Switching Times Summary Part III: Digital Electronics Chapter 16: MOSFET Digital Circuits 16.0 Preview 16.1 NMOS Inverters 16.2 NMOS Logic Circuits 16.3 CMOS Inverter 16.4 CMOS Logic Circuits 16.5 Clocked CMOS Logic Circuits 16.6 Transmission Gates 16.7 Sequential Logic Circuits 16.8 Memories: Classification and Architectures 16.9 RAM Memory Cells 16.10 Read-Only Memory 16.11 D/A Converters 16.12 A/D Converters 16.13 Summary Problems Chapter 17: Bipolar Digital Circuits 17.0 Preview 17.1 Emitter-Coupled Logic (ECL) 17.2 Modified ECL Circuit Configurations 17.3 Schottky Transistor-Transistor Logic 17.4 BiCMOS Digital Circuits 17.5 Summary Problems Appendices

A 1.4 V Supply CMOS Fractional Bandgap Reference

Abstract: This paper describes a bandgap reference that outputs a fraction of the silicon bandgap voltage. To simplify the design of an internal operational amplifier, the reference drives the base voltages on substrate transistors through unity-gain buffers to a fraction of a diode drop. With a 1.4 V supply, the reference produces an output of about 858 mV, which varies by 1.28 mV from -20degC to 100degC. It dissipates 162 muW and occupies 1.2 mm2 in 0.35 mum CMOS.

Super Class-AB OTAs With Adaptive Biasing and Dynamic Output Current Scaling

Abstract: A new family of single-stage super Class-AB operational transconductance amplifiers (OTAs) suitable for low-voltage operation and low power consumption is presented. Three novel topologies are proposed featuring simplicity and compactness. They are based on the combination of adaptive biasing techniques for the differential input stage and nonlinear current mirrors for the active load that provide additional dynamic current boosting. The OTAs have been fabricated in a standard 0.5-mum CMOS process. Experimental results show a greatly improved slew rate by factors 30-60 and gain-bandwidth product by factors 11.5-17 when compared to a classical Class-A OTA. The circuits are operated at plusmn1-V supply voltage with only 10 muA of bias current

Circuit and method for RF power amplifier power regulation and modulation envelope tracking

Abstract: A power amplifier receives an input signal and generates an amplified output signal. A switching converter generates a regulated voltage and performs power control for the power amplifier. A linear amplifier performs modulation envelope control for the power amplifier. The switching converter may be coupled in series with the linear amplifier, and this circuit may operate in one of multiple modes. For example, the linear amplifier may output a tracked voltage to the power amplifier in GSM/polar EDGE mode, and the switching converter may output the regulated voltage to the power amplifier in WCDMA/UMTS mode. The linear amplifier could also output the tracked voltage in both modes, and a selector could select the appropriate feedback voltage for the switcher. The switching converter could also provide the regulated voltage directly to the power amplifier, and the linear converter could adjust a bias of the power amplifier to provide envelope tracking.

A CMOS Chopper Offset-Stabilized Opamp

Abstract: In this paper, an offset-stabilized operational amplifier is described. The amplifier employs a chopper amplifier in a low frequency path to cancel the offset of a wide-bandwidth amplifier. A sample-and-hold circuit is used to reduce the chopper ripple, and the low frequency path is also offset-stabilized to further reduce the residual offset. The amplifier has less than 1.5 offset at a 16-kHz chopper frequency, a unity gain frequency of 1.3 MHz with a 50-pF load, and draws 700 from a 5-V supply. The amplifier was realized in a 0.7 CMOS process, and has an effective chip area of 3.6.

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

Abstract: Design procedures for three-stage CMOS operational transconductance amplifiers employing nested-Miller frequency compensation are presented in this paper. After describing the basic methodology on a Class-A topology, some modifications, to increase swing, slew-rate and current drive capability, are subsequently discussed for a Class-AB solution. The approaches developed are simple as they do not introduce unnecessary circuit constraints and yield accurate results. They are hence suited for a pencil-and-paper design, but can be easily integrated into an analog knowledge-based computer-aided design tool. Experimental prototypes, designed in a 0.35-mum technology by following the proposed procedures, were fabricated and tested. Measurement results were found in close agreement with the target specifications

Negative Group Delay Circuit for Feed-Forward Amplifier

Abstract: We present a design and an implementation of a negative group delay circuit, which consists of lumped parameter element. It is very small and simple circuit. The circuit is composed of three resonators with resisters, which are arranged to pi type circuit to improve the reflection. We discuss the principle of a negative group delay circuit and apply the circuit to the feed-forward amplifier. It is confirmed that the delay line of the distortion cancellation loop is shortened 40% by connecting the circuit to the driver stage of the error amplifier. The efficiency of the feed-forward amplifier has been improved from 9% to 12%.

Pulse wave measuring device

Abstract: A pulse-wave measurement apparatus includes a pressure detecting capacitor (CX) which changes its capacitance according to the pressure within an artery; an operational amplifier (G1) which is connected at its inverting input terminal to one end of the pressure detecting capacitor (CX) and also is connected at its non-inverting input terminal to a reference voltage; a charge transfer capacitor CF which is connected at its one end to the inverting input terminal of the operational amplifier (G1) and also is connected at the other end to the output of the operational amplifier (G1); a switch (SW1) which is connected at its one end to the inverting input terminal of the operational amplifier (G1); and a voltage setting portion (54) which is connected at its one end to the other end of the switch (SW1) and also is connected at the other end to the output of the operational amplifier (G1), the voltage setting portion (54) being adapted to connect the other end of the switch (SW1) to the output of the operational amplifier (G1) or to disconnect the other end of the switch (SW1) from the output of the operational amplifier (G1) and applies a predetermined voltage to the other end of the switch (SW1).

Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor

Abstract: This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances

A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse

Abstract: Power and area saving concepts such as operational amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 muW/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp settling with low power-consumption. The prototype achieves 9.2/8.8 effective number of bits (ENOB) for 1- and 20-MHz inputs at 50 MS/s. The ADC works within the temperature range of 0deg to 85 degC and the supply voltage from 1.62 to 1.96 V with little measured loss in the ENOB. The chip consumes 18 mW (11 mW for the analog portion of the ADC and 7 mW for the rest including buffers) at 1.8 V, and the active area occupies 1.1 times 1.3 mm2 using a 0.18-mum complementary metal oxide semiconductor (CMOS) process.

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

Abstract: An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.

Analytical Synthesis of Low-Sensitivity High-Order Voltage-Mode DDCC and FDCCII-Grounded R and C All-Pass Filter Structures

Abstract: The difficulty of realizing the operations of addition and subtraction of a voltage-mode signal renders two special active elements, namely, differential difference current conveyors (DDCCs) and fully differential current conveyors (FDCCIIs), both of which have the ability to perform the operations of addition and subtraction, to become very important for voltage-mode analog filter design. Note that, for the design of operational transconductance amplifier and capacitor (OTA-C) filters, the recently reported analytical synthesis methods (ASMs) have been shown to be very effective for achieving simultaneously the three criteria, namely, all capacitors being grounded, the use of the minimum number of active and passive components, and the use of single-ended input OTAs. However, none of the ASMs uses DDCCs and FDCCIIs in the design of voltage-mode filters. In this paper, a method of realizing DDCC and FDCCII-based all-pass filter structures with either equal capacitances or equal conductances through a new ASM is presented. Only n current conveyors (the least number of active components), n grounded capacitors, and grounded resistors (the minimum number of passive components) are used for realizing an nth-order voltage-mode all-pass filter structure. Moreover, the new all-pass filter structure synthesized by the new ASM achieves very low individual as well as near-null group sensitivities just as in the case of the passive LC ladder filters, has very low power consumption, a low component spread for equal denominator conductance design, and a high input impedance which is attractive from the point of view of cascadability. Finally, H-Spice simulations, using 0.35-mum process and plusmn1.65-V supply voltages, are included and validate theoretical predictions.

Enhancing general performance of folded cascode amplifier by recycling current

Abstract: A modification to the conventional folded cascode transconductance amplifier is proposed. The proposed amplifier has the benefit of achieving a given set of design specifications while consuming a fraction of the power compared to the conventional folded cascode. Moreover, the proposed modification is robust even for low voltage applications.

Concurrent Dual-Band Class-E Power Amplifier Using Composite Right/Left-Handed Transmission Lines

Abstract: A concurrent dual-band class-E power amplifier using composite right/left-handed transmission lines (CRLH TLs) is proposed. Dual-mode operation is achieved by using the frequency offset and nonlinear phase slope of CRLH TLs for the matching network of power amplifiers. The frequency ratio of two operating frequencies is not necessarily an integer. Two operating frequencies are chosen as 836 MHz and 1.95 GHz for simulation. Three methods for designing a CRLH TL power amplifier are proposed. The measured results based on one method show that output powers of 22.4 and 22.2 dBm were obtained at 800 MHz and 1.70 GHz, respectively. In terms of maximum power-added efficiency, we obtained 42.5% and 42.6% at 800 MHz and 1.70 GHz, respectively.