Showing papers on "Parasitic capacitance published in 1997"

Self-capacitance of inductors

Abstract: A new method for predicting the stray capacitance of inductors is presented. The method is based on an analytical approach and the physical structure of inductors. The inductor winding is partitioned into basic cells-many of which are identical. An expression for the equivalent capacitance of the basic cell is derived. Using this expression, the stray capacitance is found for both single- and multiple-layer coils, including the presence of the core. The method was tested with experimental measurements. The accuracy of the results is good. The derived expressions are useful for designing inductors and can be used for simulation purposes.

Capacitive sensitive switch method and system

Abstract: A touch sensor switch that responds to touching, or even to the proximity of an object, is disclosed. The switch includes a number of capacitance elements, or touch pads, that produce an effective capacitance dependent upon the physical proximity of the object. A microcontroller under control of a program stored in a read-only memory causes its I/O port to set a transient voltage on each capacitance element as a logic level. Each transient voltage is at variance with the capacitive element's preferred voltage level. The program then reads the I/O port, and hence the logic levels of the capacitance elements, as the capacitive elements revert to their preferred voltage levels, and calculates the proximity of the object, or touching, from relationships among recorded signals. The circuit may also be embodied in an application specific integrated circuit.

Surface micromachined solenoid inductors for high frequency applications

Abstract: As operation frequencies and performance requirements of wireless devices increase, the resultant demands on the performance of passive components also increase. Miniaturization of inductive components for high frequency has been a key research area to address this issue; however, in general, miniaturized integrated inductors can suffer from low Q factors and/or self-resonant frequencies when compared to their discrete counterparts. The most popular geometries for integrated inductors have been meander types or spiral types, whereas most macro scale inductors are solenoid types. In this research, a modified geometry of a solenoid type inductor using a surface micromachining technique is proposed. This inductor has an air core for high frequency operation and an electroplated copper coil to reduce the series resistance. An important feature of the proposed inductor geometry is the introduction of an air gap between the substrate and the conductor coil in order to reduce the effects of the substrate dielectric constant. This air gap can be realized using a polyimide sacrificial layer and a surface micromachining technique. Therefore, the resulting inductor can have less substrate-dependent magnetic properties, less stray capacitance, and higher Q-factor. A preliminary measurement result shows that this inductor has high Q-factor and stable inductance over a wide range of operating frequency.

A physical, yet simple, small-signal equivalent circuit for the heterojunction bipolar transistor

Abstract: A physical, yet simple, small-signal equivalent circuit for the heterojunction bipolar transistor (HBT) is proposed. This circuit was established by analyzing in detail the physical operation of the HBT. The model verification was carried out by comparison of the measured and simulated S- and Z-parameters for both passive (reverse-biased) and active bias conditions. A feature of this model is that it uses a direct extraction method to determine the parasitic elements, in particular, the parasitic capacitances. The excellent agreement between the measured and simulated parameters was verified all over the frequency range from 0.25 to 75 GHz.

Printed circuit board (PCB) including channeled capacitive plane structure

Abstract: Electrical potentials and very high frequency (VHF) currents in a circuit board are controlled by patterning the power plane of a multiple layered, capacitive plane printed circuit board in selected geometric patterns. The selected geometric patterns, both simple and complex, control voltages and currents by channeling the capacitance capacity for usage directed to a particular integrated circuit or circuits, isolated to a particular integrated circuit or circuits, or shared between integrated circuits. Accordingly, the capacitive planes including the geometrically patterned power plane are channeled capacitive planes (CCP) that are formed on multiple layers of a single printed circuit board to support flexible, three-dimensional control of VHF electrical currents.

High-speed characteristics of low-optical loss oxide-apertured vertical-cavity lasers

Abstract: We characterize the high-speed modulation properties of thin-oxide-apertured vertical-cavity lasers. The modulation response scales with device diameter due to the negligible optical scattering loss present in these devices. A small diameter laser of 3.1 /spl mu/m has a maximum 3-dB bandwidth of 15.2 GHz at a bias of only 2.1 mA. Modeling indicates a no-parasitic bandwidth of 18.2 GHz at this current level, with an intrinsic 3-dB bandwidth limit of 45 GHz due to gain compression. The present devices are limited by parasitic capacitance across the thin oxide layer.

Integrated tunable inductance network and method

Abstract: An integrated, tunable inductance network features a number of fixed inductors fabricated on a common substrate along with a switching network made up of a number of micro-electromechanical (MEM) switches. The switches selectably interconnect the inductors to form an inductance network having a particular inductance value, which can be set with a high degree of precision when the inductors are configured appropriately. The preferred MEM switches introduce a very small amount of resistance, and the inductance network can thus have a high Q. The MEM switches and inductors can be integrated using common processing steps, reducing parasitic capacitance problems associated with wire bonds and prior art switches, increasing reliability, and reducing the space, weight and power requirements of prior art designs. The precisely tunable high-Q inductance network has wide applicability, such as in a resonant circuit which provides a narrow bandwidth frequency response which peaks at a specific predetermined frequency, making possible a highly selective performance low noise amplifier (LNA), or in an oscillator circuit so that a precise frequency of oscillation can be generated and changed as needed.

Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance

Abstract: Adding on-chip decoupling capacitance has become a popular method to reduce dI/dt noise in integrated circuits. The most area-efficient realization of on-chip capacitance in a standard CMOS process is to use the gate capacitance of MOS transistors. In this paper, the inevitable parasitic resistance of an MOS transistor is estimated, which is important for two reasons. The resistive noise caused by this parasitic must be kept low, and, if properly sized, this resistance can be used to dampen potential resonance oscillations.

Capacitance type sensor interface circuit

Abstract: In an interface circuit connected to a capacitance type sensor having two sets of capacitors C1 and C2 whose capacitances are varied, this interface circuit is equipped with an OP amplifier A1 where a feedback/sampling capacitor C3 is connected between its output terminal and its inverting input terminal; and a holding capacitor C4 connected between a non-inverting terminal of the OP-amplifier A1 and a reference voltage source; one ends of the respective capacitors C1, C2, C3 are connected to the inverting input terminal of the OP amplifier A1; at timing φ1 of a switching cycle, the other ends of the respective capacitors C1, C2 are connected to a power source and the capacitor C3 is shortcircuited; at timing φ2 thereof, the other ends of the capacitors C1, C2 and an output terminal of the OP amplifier A1 are connected to the non-inverting input terminal of the OP amplifier A1; and the switched capacitor type interface interface circuit further includes: a multiplexer for sequentially connecting a plurality of the capacitance type sensors to the capacitance type sensor interface circuit in a second switching cycle having a time period longer than time periods of the switching cycles φ1 and φ2; and a plurality of sample/hold circuits whose quantity is equal to those of the plural capacitance type sensors, which are sequentially connected to the capacitive type sensor interface circuit in response to the connections of the plural capacitance type sensors in the second switching cycle.

Driver circuit device

Abstract: In the constant current drive type driver used for an LVDS (low voltage differential signal) interface, the parasitic capacitance of the package pins is charged and discharged sufficiently at a high speed to secure the high speed signal transmission operation. Further, the AC differential amplitude large enough to be received by the receiver can be obtained. The driver circuit device comprises: a transmit circuit composed of transistors (52, 53, 56, 57) for transmitting a signal by switching the signal current direction flowing through a pair of transmission lines (8, 9) connected between two output terminals (13 and 13B); and a constant current source composed of transistors (54, 75) for controlling the current value of the transmit circuit. In the idle state, only one of the two transistors (54 and 75) of the constant current source is turned on to limit the signal current flowing through the output terminals (13 and 13B). On the other hand, in the high speed signal transmission, both the transistors (54, 75) are turned on to increase the signal current flowing through the output terminals (13, 13B) to obtain a signal current of high DC LVDS level.

A simple method for on-chip, sub-femto Farad interconnect capacitance measurement

Abstract: In this letter, a sensitive and simple technique for parasitic interconnect capacitance measurement and extraction is presented. This on-chip technique is based upon an efficient test structure design that utilizes only two transistors in addition to the unknown interconnect capacitance to be characterized. No reference capacitor is needed. The measurement itself is also simple; only a dc current meter is required. Furthermore, the extraction methodology employs a self-checking algorithm to verify that the extracted capacitance value is consistent and accurate. The technique is demonstrated by extracting the capacitance of a single crossover between a Metal 1 line and a Metal 2 of 0.44 fF. The resolution limit is dominated by the matching of the minimum sized transistors used for the test structure. We estimate this resolution limit to be about 0.03 fF.

Common electrode voltage driving circuit for a liquid crystal display

Abstract: A control circuit for providing a common electrode voltage for a liquid crystal display dynamically controls the voltage applied to the common electrode according to various factors that effect the capacitance across the liquid crystal layer. The common electrode control circuit dynamically adjusts the common electrode voltage according to the current maximum and minimum display voltages. In addition, the common electrode control circuit adjusts the common electrode voltage according to the gate-to-source parasitic capacitance, as well as temperature fluctuations. Thus, the control circuit compensates for the most significant factors which may cause the inadvertent accumulation of a charge across the liquid crystal layer.

Method and apparatus for characterized parasitic capacitance between integrated-circuit interconnects

Abstract: A method and apparatus for characterizing dimensions and parasitic capacitance between integrated-circuit interconnects are disclosed. The apparatus is a test structure including at least two substantially identical oscillators, at least two substantially identical counters, and a pulse generator. Each of the oscillators is connected to an integrated-circuit interconnect. Each of the counters is coupled to a respective oscillator. The pulse generator is utilized to inject a series of fixed-length clock pulses to each of the oscillators such that the parasitic capacitance of the integrated-circuit interconnects can be characterized by the ratio of oscillation periods of the oscillators to parasitic capacitances of the integrated-circuits.

Use of gas as low-k interlayer dielectric in LSI's: Demonstration of feasibility

Abstract: Reduction of the wire capacitance in LSI's has become an issue of the utmost importance since the wire parasitic capacitance plays a significant role in determining both chip speed and power. Low dielectric constant materials such as SiOF (k=3.3) are already in use in manufacturing, while other materials with lower dielectric constants (k=2.0/spl sim/3.0) are under development. Technology for further reduction of the dielectric constant, however, has not been reported so far. In this paper, we propose a gas-dielectric process that has the potential to achieve almost the minimum physically possible value for the dielectric constant: 1.0. The conceptual feasibility of the process is demonstrated, and basic process characterization data are presented. In addition, issues to be considered when integrating the proposed process into LSI manufacturing are identified, and work currently in progress addressing these issues is discussed.

Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage

Abstract: A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.

Inductor devices using substrate biasing technique

Abstract: Inductors used for impedance matching in the radio frequency integrated circuits is disclosed. In the integrated inductor device according to the present invention, an additional electrode is arranged in surroundings of an inductor metal line, and the reverse bias voltage is applied to the region between the substrate and the electrode so as to form a depletion layer. Therefore, the substrate biasing is effected and thus an inductor having improved performance can be formed by decreasing the parasitic capacitance between the inductor metal line and the substrate. The present invention can also be applied to another semiconductor device having metal lines and pads.

Multi-resonant soft switching snubber network for DC-to-DC converter

Abstract: A family of DC-to-DC converters includes a multi-resonant snubber network connected in parallel with a power switching device. The multi-resonant snubber network includes an auxiliary switch that is connected to transfer the energy from a parasitic capacitance of the power switching device into a resonant inductor and to achieve zero-voltage turn-on of the power switching device. An additional resonant path is included in the snubber network to achieve zero-voltage turn-off of the auxiliary switch and the power switching device.

Quasi-saturation capacitance behavior of a DMOS device

Abstract: This paper reports a simulation study on the capacitance characteristics of a double-diffused metal-oxide semiconductor (DMOS) device operating in the quasi-saturation region. From the analysis, the capacitance effect of the gate oxide upon the drift region cannot be modeled as an overlap capacitance, because the drain-gate/source-gate capacitances of the DMOS device may exceed the gate-oxide capacitance due to the larger voltage drop over the gate oxide than the change in the imposed gate bias when entering the quasi-saturation region. This effect can be the explanation for the plateau behavior in the gate charge plot during turn-on and turn-off of the DMOS device. Based on the small-signal equivalent capacitance model, the accumulated charge in the drift region below the gate oxide may thoroughly associate with the drain terminal in the prequasi-saturation region and with the source terminal in the quasi-saturation region.

Charge pump circuit for use in a phase locked loop

Abstract: A charge pump circuit in a phase locked loop comprises a main circuit block and an excess current cancel block for canceling a spike current. The spike current is generally supplied by a parasitic capacitance in the main circuit block and generates a jitter in the output of the phase locked loop. The excess current cancel block supplies or drains a cancel current which is substantially equal to the spike current but flows in a reverse direction.

Charge pump circuit and method

Abstract: A circuit and method produce a pump current (I p ) at the output (31) of a charge pump (26). A switching transistor (32, 35) is coupled at a node (38, 39) to a current source transistor (33, 34) to produce the pump current at a specified magnitude in response to an input pulse (V PU , V PD ). A charge is stored on a parasitic capacitance of the node. A charge conduction path (42, 43) is coupled to the node and enabled on one transition edge of the input pulse to alter the charge by routing to a discharge node (45) to reduce charge flowing to the output as an error current. The charge conduction path is disabled on the other transition edge of the input pulse to isolate the node from the output.

Characteristics of an integrated spiral inductor with an underlying n-well

Abstract: Effects due to presence of n-wells with bias and no bias under spiral inductors are described. Inductors with underlying n-wells are fabricated using a 0.8-/spl mu/m CMOS process. S-parameters are measured at different n-well bias conditions and equivalent circuit parameters are extracted and compared. The results show that when the n-well-to-substrate junctions are reverse biased parasitic capacitance associated with the inductors can be reduced approximately by a factor of 2 and the peak quality factor (Q) can be increased by /spl sim/10%. This reduction in the parasitic capacitance should enable widening of the inductor metal traces to increase the Q at low frequencies while keeping the parasitic capacitance and self-resonance frequency constant.

Fmax enhancement of dynamic threshold-voltage MOSFET (DTMOS) under ultra-low supply voltage

Abstract: The high frequency characteristics of DTMOS are described here for the first time Our DTMOS has a small parasitic resistance due to an optimized Co salicide technology and a small parasitic capacitance due to a reduction in the overlapped region between the gate and drain, which is achieved by gate poly-Si oxidation before LDD implantation We obtained an Ft of 78 GHz and an Fmax of 37 GHz for a 01-/spl mu/m-Leff DTMOS even at a supply voltage of 07 V We also noted an Fmax enhancement of 15 times compared to that of a conventional SOI MOSFET, which is attributed to a high transconductance and a large output resistance

A new high efficiency CMOS voltage doubler

Abstract: A charge pump cell is used to make a voltage doubler using improved serial switches. The PMOS transistor used for the serial switch is analyzed and a model suitable for simulation is described. The importance of capacitors is shown with plots of efficiency versus load and stray capacitance. Several problems arising at low voltage or high frequency are developed and some optimizations are presented. The substrate current is totally suppressed by the technique of bulk commutation. An efficiency of 94% has been reached using external capacitors.

Method for measuring yield and moisture

Abstract: A method and apparatus for measuring at least one parameter including mass flow rate or moisture content of material moved by a conveyor are disclosed herein. The method includes the steps of applying an electric field to the material using a non-intrusive sensor assembly, generating signals related to the dielectric value of the material, and processing the signals to determine the parameter. The apparatus includes a capaciflector sensor assembly located along a surface of the conveyor to generate an electric field applied to the material and a processing circuit to determine the parameter based upon the signals output from the sensor assembly. The sensor assembly includes a first conductor spaced between a stationary member of the conveyor and the material, and a second conductor spaced between the first conductor and the stationary member to act as a shield for reducing parasitic capacitance between the first conductor and a reference plane. The first conductor forms a first electrode of a sensor capacitor and the material forms a second electrode, and the capacitance depends on the parameters of the material. A cover may be located between the sensor assembly and material. The processing circuit performs a frequency analysis over any number of frequencies to determine the mass flow rate, moisture content or type of material, and the conveyor's speed.

A 2 MHz, 2 kW voltage-source inverter for low-temperature plasma generators: implementation of fast switching with a third-order resonant circuit

Abstract: This paper presents a specially designed third-order resonant circuit intended to achieve fast switching operation for a voltage-source series-resonant inverter using four MOSFETs. The third-order resonant current superimposed on a sinusoidal load current helps to quickly charge or discharge the output capacitance of each MOSFET. This results not only in a reduction of the commutation period which is required to turn the MOSFET on and off, but also in an improvement of the displacement factor at the output of the inverter. Moreover, the third-order resonant circuit acts as a low-pass filter to suppress the parasitic oscillation between line inductance and stray capacitance. The viability and effectiveness of the third-order resonant circuit is verified by a 2 MHz 2 kW prototype inverter developed for a low-temperature plasma generator.

Printed circuit board having an embedded capacitor

Abstract: A circuit board having a printed capacitor whose capacitance is easily adjusted includes a plurality of through-holes arranged in arrays and electrically connected to each other via conductive films. Therefore, first and second electrode portions are arranged to oppose each other, and form a printed capacitor. The capacitance of the capacitor can be adjusted by the number and diameter of through-holes, and the interval between each two adjacent through-holes. Therefore, even when a large-capacitance capacitor is to be formed, the printed capacitor can be rendered compact.

Printed circuit board having a well structure accommodating one or more capacitor components

Abstract: Printed Circuit Board fabrication costs are decreased, and device placement densities are increased by the use of well structures designed for receiving components such as capacitors on portions of the PCB directly beneath integrated circuit packages having very low vertical profiles. With such an arrangement it is possible to use newer low profile packages and still place a capacitor under the integrated circuit package for reduced area consumption and improved inductance and circuit cycle times. Further advantages of the present arrangement include a reduction in the number of vias that need to be drilled in the PCB to make capacitor attachments, a consequent improvement in PCB inductance and parasitic capacitance, and improved electrical properties for voltage reference planes and routing layers.

Radio frequency diagnostics for plasma etch systems

Abstract: Selective etching of silicon dioxide over silicon is a frequently used process in the manufacture of semiconductor devices. Limited diagnostic capabilities have forced plasma etch systems to rely on traditional statistical process control and recipes. With the addition of in situ measurements, however, automatic feedback control could be employed for control of the process variables. This paper focuses on the implementation and installation of a radio frequency power sensor suitable for advanced process control of plasma etching. The sensor measured information about the direct current bias voltage, radio fequency voltage, current, and phase angle at three locations in the power delivery system: before the matching network, after the matching network, and at the lower electrode. Matching network efficiency and transmission line analysis were used to transform between each measurement. This information showed the importance of accurate characterization of stray capacitance and inductance in the power delivery system. Plasma parameters of impedance, delivered power, sheath thickness, and sheath capacitance were computed using simple equivalent circuit models for the plasma discharge. Measurement of the fundamental and harmonic components of the voltage, current, and phase showed that the power generated in the plasma at the harmonic frequencies was approximately 3% of the generator power. Amplitudes of harmonic voltage matched analytical predictions.

A compact-charge LDD-MOSFET model

Abstract: A compact-charge LDD-MOSFET model, based on an analytical surface potential formulation at source and drain has been derived and implemented in the circuit simulator SABER for all channel length and width down to deep submicrometer. Besides well-known short- and narrow-channel effects, the model includes additional charge effects around the threshold voltage as well as a bias dependent charge description of the overlap LDD(S)-region. These additional capacitance effects are not considered in conventional submicrometer transistor models although they domain the capacitance characteristic with further downscaling. If not taken into account, simulation errors of, e.g., up to 50% in the frequency of a 0.3 /spl mu/m CMOS ring oscillator or over 100% in the 3 dB critical frequency of amplifier circuits can result.

An improved small-signal equivalent circuit model for III-V nitride MODFET's with large contact resistances

Abstract: A small-signal equivalent circuit model of III-V nitride MODFET's is presented. The metal-semiconductor ohmic contacts were modeled as a transmission line, as parasitic Z-elements cannot be modeled as a simple resistor/inductor discrete circuit due to high contact resistances. The model describes the highly resistive contacts with a good accuracy.