Showing papers on "Parasitic element published in 2012"

Reducing Mutual Coupling of MIMO Antennas With Parasitic Elements for Mobile Terminals

Abstract: Mutual coupling is a critical problem in the design of MIMO antennas because it deteriorates the performance of MIMO systems, which not only affects the antenna efficiency but also influences the correlation. Therefore, in this paper, using parasitic elements to reduce mutual coupling is studied. By adding parasitic elements a double-coupling path is introduced and it can create a reverse coupling to reduce mutual coupling. As an example, a dual-slot-element antenna with parasitic monopoles for mobile terminals is described. The discussion on channel capacity shows that the antenna can be considered as a good candidate for MIMO systems. Furthermore, based on the study of current distributions, it is concluded that the technique is sensitive to relative positions between parasitic elements, and relative positions between active element and parasitic element. Finally, we also extend the technique to a tri-element antenna.

A Broadband LTE/WWAN Antenna Design for Tablet PC

Abstract: A broadband yet compact antenna design applicable to tablets and laptops is proposed. The antenna provides an extensive coverage for existing and upcoming mobile communication bands. Several band broadening and antenna miniaturization techniques were employed, including the use of a parasitic element, meandered structures, branched structures and a lump component. The proposed design is planar, compact and can be fabricated via printed circuit board technology. Measurement results exhibits broad resonant bandwidth. Nearly omni-directional patterns and reasonable radiation efficiency are observed.

The Impact of Parasitic Inductance on the Performance of Silicon–Carbide Schottky Barrier Diodes

Abstract: 1200V/300A silicon carbide Schottky barrier diode (SiC SBD) and Si pin diode modules have been tested as free-wheeling diodes under conditions of clamped inductive switching over a temperature range between -40 °C and 125 °C. Over the temperature range, the turn-OFF switching energy increases by 100% for the Si pin diode, whereas that of the SiC diode is temperature invariant and is 50% less than that of the Si pin diode at 125°C. However, the SiC SBD suffers from ringing/oscillations due to an underdamped response to an RLC circuit formed among the diode depletion capacitance, parasitic inductance, and diode resistance. These oscillations contribute to additional power losses that cause the SiC SBDs to be outperformed by the Si pin diodes at -40 °C and 0 °C. The higher depletion capacitance and lower series resistance of the SiC SBD contribute to a lower damping factor compared to the Si device. Furthermore, the positive temperature coefficient of the ON-state resistance in silicon contributes to better damping at high power levels, whereas the temperature invariance of the ON-state resistance in SiC means the oscillations persist at high temperatures. SPICE simulations and experimental measurements have been used to validate analytical expressions that have been developed for the circuit damping and oscillation frequency.

On impedance spectroscopy analysis of nonideal heterojunctions

Abstract: A quantitative analysis of the impedance of nonideal heterojunctions was carried out taking into consideration the effects of series resistance, shunt resistance, parasitic inductance and electrically active interface traps. A new approach is proposed to determine the energy distribution of surface state density and to calculate the actual value of barrier capacitance of heterojunctions on the basis of the analysis of their complex impedance–voltage characteristics.

Electrical characterization of a-InGaZnO thin-film transistors with Cu source/drain electrodes

Abstract: We analyzed the effects of Cu source/drain (S/D) electrodes on the performance of a-InGaZnO (a-IGZO) thin-film transistors (TFTs). Owing to the Cu migration, the parasitic resistance was as low as 10 Ω cm with small current transfer length. Based on the transfer characteristics, we found that VDS dependent Cu migration creates donor-like deep and tail states in the sub-bandgap region. The feasibility of Cu S/D electrodes for a-IGZO TFTs using inverter circuits indicates that fabrication of high performance circuits is possible by controlling the Cu electro-migration.

Accurate Extraction Method of Reverse Recovery Time and Stored Charge for Ultrafast Diodes

Abstract: This letter presents a novel extraction method to accurately determine a reverse recovery time and a stored charge for ultrafast diodes. To obtain this, a test circuit to measure those parameters was accurately modeled by considering an inductance and a parasitic resistance, which are inherently embedded in the test circuit and lead to oscillation. The experimental results showed that the corrected reverse recovery time was reduced by 1.2 ns for an Si fast recovery diode, while by 6.8 ns for an SiC Schottky barrier diode, compared to their measured reverse recovery time.

Impact of gate resistance in graphene radio frequency transistors

Abstract: The effect of gate resistance on the high frequency device properties of graphene transistors is explored. Decreasing this resistance does not alter the current gain cutoff frequency (fT), but it does allow for the power gain cutoff frequency (fmax) to be increased. Analysis of this effect reveals that the relative rate of change between fT and fmax is most sensitive to the relationship between the parasitic resistance in the device channel and the output conductance, a manifestation of device scaling in the triode regime. This result underlies the importance of a small output conductance in the scaling of graphene transistors.

Influence of Parasitic Capacitance on Output Voltage for Series-Connected Thin-Film Piezoelectric Devices

Abstract: Series-connected thin film piezoelectric elements can generate large output voltages. The output voltage ideally is proportional to the number of connections. However, parasitic capacitances formed by the insulation layers and derived from peripheral circuitry degrade the output voltage. Conventional circuit models are not suitable for predicting the influence of the parasitic capacitance. Therefore we proposed the simplest model of piezoelectric elements to perform simulation program with integrated circuit emphasis (SPICE) circuit simulations). The effects of the parasitic capacitances on the thin-film Pb(Zr, Ti)O3, (PZT) elements connected in series on a SiO2 insulator are demonstrated. The results reveal the negative effect on the output voltage caused by the parasitic capacitances of the insulation layers. The design guidelines for the devices using series-connected piezoelectric elements are explained.

Characterization and modeling of schottky diodes up to 110 ghz for use in both flip-chip and wire-bonded assembled environments

Abstract: This paper presents a wideband model, from Direct Current (DC) to W band, for a single Anode Schottky Diode based on a commercial VDI chip. Difierent measurements have been performed to obtain a complete large-signal equivalent circuit model suitable for the device under consideration up to 110GHz, and for its integration in planar circuits. The modeling has been done using a combination of DC measurements, capacitance measurements, and RF scattering measurements. The test structure for on-wafer S- parameter characterization has been developed to obtain an equivalent circuit for Coplanar to Microstrip (CPW-Microstrip) transitions, then verifled with 3D Electromagnetic (EM) tools and flnally used to de- embed device measurements from empirical data results in W band. 3D EM simulation of the diodes was used to initialize the parasitic parameters. Those signiflcant extrinsic elements were combined with the intrinsic elements. The results show that the proposed method is suitable to determine parameters of the diode model with an excellent flt with measurements. Using this model, the simulated performance for a number of diode structures has given accurate predictions up to 110GHz. Some anomalous phenomena such as parasitic resistance dependence on frequency have been found.

Switching loss reduction in converter modules

Abstract: The invention relates to converters for converting a DC input voltage a DC or an AC output voltage. The converters have a parasitic inductance. The converters comprise at least one switching element connected to an input terminal for providing a first voltage at an output terminal. In order to allow temporarily storing, in a capacitor, energy induced by the parasitic inductance when switching OFF the switching element, a first series circuit of a diode and a capacitor is provided in the converter, wherein the diode is coupled to the one input terminal. An active circuit coupled in parallel with the diode enables controlling the release of temporarily stored energy from the capacitor of the first series circuit.

Intrinsic parameter extraction of a-InGaZnO thin-film transistors by a gated-four-probe method

Abstract: We analyzed the intrinsic electrical characteristics of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) using a gated-four-probe method. Based on the back channel potential, the extraction of intrinsic field-effect mobility (μFEi) and parasitic resistance in source (Rs) and drain (Rd) electrodes was performed especially for low VGS and VDS conditions. The resulting μFEi showed typical VGS dependency of amorphous semiconductor TFTs. However, Rs and Rd showed that there can be non-uniformity in source/drain parasitic resistance, which indicates that a separate analysis of the parameters of each electrode is essential for further improvement of the performance of a-IGZO TFTs.

Antenna apparatus including dipole antenna and parasitic element arrays for forming pseudo-slot openings

Abstract: In each parasitic element array, each of parasitic elements has a strip shape substantially parallel to a longitudinal direction of a dipole antenna, and the parasitic elements are formed at predetermined intervals. For example, the interval is set to be equal to or smaller than ⅛ of a wavelength λ of a high-frequency signal to be fed to a feeder line. The parasitic element arrays are arranged so as to form a plurality of pseudo-slot openings that allow a radio wave from the dipole antenna to propagate therethrough as magnetic currents.

Wideband ZVS half-bridge circuit for piezoelectric transformers with small inductance

Abstract: A wideband zero-voltage-switching (ZVS) half-bridge circuit for piezoelectric transformers is introduced. The proposed circuit topology is the extension of the inductor-less half-bridge driver for the piezoelectric transformers. Two auxiliary shunt circuits are connected to the input terminal PT to ensure the ZVS condition in a wide bandwidth. Each auxiliary shunt circuit includes a diode, a switch and an inductor. The auxiliary inductor exhibits a small inductance and is not in the path of the major power flow, thus it can be implemented by the parasitic inductance of the connection wires or by PCB tracks. A 80kHz piezoelectric transformer was tested by the proposed circuit from 20 to 160 kHz to verify the ZVS condition.

Semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure

Abstract: Disclosed is a semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure. The structure comprises a semiconductor device (e.g., a two-terminal device, such as a PN junction diode or Schottky diode, or a three-terminal device, such as a field effect transistor (FET), a bipolar junction transistor (BJT), etc.) and a dielectric layer that covers the semiconductor device. A contact extends vertically through the dielectric layer to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). A contact sidewall spacer is positioned on the contact sidewall and incorporates an airgap. Since air has a lower dielectric constant than other typically used dielectric spacer or interlayer dielectric materials, the contact size can be increased for reduced parasitic resistance while minimizing corresponding increases in parasitic capacitance or the probability of shorts.

Wireless electronic devices with multiple curved antennas along an end portion, and related antenna systems

Abstract: Wireless electronic devices (100) may include a backplate (400) and first and second curved antennas (210, 220) spaced apart from each other along an end portion of the backplate Each of the first and second curved antennas may include a radiating element (416, 426) and a parasitic element (414, 424) electrically coupled to the radiating element Related systems are also described

Amplifier with reduced source degeneration inductance

Abstract: Techniques for reducing undesired source degeneration inductance are disclosed. In an exemplary design, an apparatus includes first and second connections. The first connection includes a first parasitic inductance acting as a source degeneration inductance of an amplifier. The second connection includes a second parasitic inductance magnetically coupled to the first parasitic inductance to reduce the source degeneration inductance of the amplifier. The amplifier (e.g., a single-ended power amplifier) may be coupled to circuit ground via the first connection. An impedance matching circuit may be coupled to the amplifier and may include a circuit component coupled to circuit ground via the second connection. The first connection may be located sufficiently close to (e.g., within a predetermined distance of) the second connection in order to obtain the desired magnetic coupling between the first and second parasitic inductances.

A 6.5kV wire-bondless, double-sided cooling power electronic module

Abstract: A 6.5kV, wire-bondless power electronics module with a double-sided cooling is proposed and evaluated. A direct solder attachment is employed to minimize parasitic circuit elements and increase current handling capability as well as to enable a double-sided cooling capability with mechanical robustness. Finite element simulations were performed to investigate the thermal performance, critical breakdown voltage and mechanical stresses of the power electronic module. The active devices in the proposed modules were demonstrated to withstand a 6.5kV breakdown voltage with a reasonable leakage current. The parasitic inductance is also modeled and compared between wire-bonded and wire-bondless power module. The mechanical and electrical performance of the power module agreed well with simulation results.

Parameter extraction method of AlGaN/GaN HEMT small-signal model

Abstract: The invention relates to a parameter extraction method of an AlGaN/GaN HEMT small-signal model, belonging to the technical field of integrated circuits. The parameter extraction method is improved on the basis of the traditional parameter extraction method. An open-circuit de-embedding graph is adopted to extract peripheral parasitic parameters. A grid-terminal Schottky resistor Rgs is introduced to extract parasitic resistance and inductance, and a drain-terminal delay factor tau(ds) is introduced to extract internal intrinsic parameters so as to ensure that the extracted parameters are positive values and have physical significance, thus S11 and S22 in S parameters of small-signal parameters are improved. In the parameter extraction process, two items Ri and Cds of the sum are frequently easy to generate a negative value, and the introduction of the Rgs and tau(ds) basically eliminates the possibility of occurrence of the negative value, thus the accuracy of the extracted parameters is greatly improved through the improvements.

Performance Analysis of Junctionless Transistors Based on Monte Carlo Simulation

Abstract: A junctionless (JL) transistor has no pn junctions and has a number of advantages to fabricate ultrashort-channel metal–oxide–semiconductor field-effect transistors. In this paper, we study the electron transport in JL transistors based on a Monte Carlo simulation. We demonstrate that high channel doping will not degrade the drive current seriously, because ionized impurities scatter electrons mostly forward, and thus there is less chance for scattered electrons to return back to the source. We also find that smaller parasitic resistance in the source of a JL transistor also contributes to achieve high drive current.

The optimum device parameters for high RF and analog/MS performance in planar MOSFET and FinFET

Abstract: In planar MOSFET, the optimization of finger length should be carried out with considering f T , f max and flicker noise because the noise degradation at STI edge effect appears below 1µm. In FinFET, the optimization of not only finger length but also the distance between gate and source, drain contact region and fin pitch are necessary to reduce parasitic resistance and capacitance. According to our measurement results, the flicker noise of FinFET decreases with scaling of fin width and it is possible to satisfy the 24nm technology node requirement in ITRS roadmap 2011 at fin width below 20nm.

Temperature detection method and device with improved accuracy and conversion time

Abstract: Temperature accuracy is improved, conversion gain is increased without increasing current density and parasitic resistance errors and other problems with conventional bandgap reference temperature sensors are eliminated by generating a signal proportional to temperature from four samples, where the signal is defined as a difference between a first difference and a second difference, the first difference comprising a difference between the second sample and the first sample, the second difference comprising a difference between the fourth sample and the third sample, and where the signal is defined to cancel parasitic components in the first, second, third and fourth samples.

Multilayer parasitic microstrip antenna array for WiMAX application

Abstract: This paper presents the design of a multilayer parasitic microstrip antenna array concerned on enhancement of gain at 58 GHz for WiMAX application The proposed structure of this project is microstrip patch antenna array which is composes of three layers using different material substrate The substrate for the first layer consists of Flame Retardant 4 (FR-4) that has thickness 16mm while the second and third layers are 3mm thickness using foam substrate The first layer is a driven element while second and third layer are 2 by 2 parasitic patch elements The multilayer microstrip antenna array was design and optimized using Computer Simulation Tool (CST) The simulation results show the enhancement of gain is increased about 623% when adding the parasitic element The gain before adding the parasitic element is 2012 dB and after adding the parasitic elements is 8656 dB The performance of the designed antenna is to test for return loss, Voltage Standing Wave Ratio (VSWR), bandwidth, directivity, radiation pattern and gain

An Improved Parasitic Capacitance Cancellation Method for Planar Differential Mode Inductor in EMI Filters

Abstract: Power semiconductor components with high switching speed are widely used in static converters. However, they produce conducted electromagnetic interferences in high frequencies. Filters are one solution for reducing the conducted emissions. However, the parasitic elements of the passive components in the EMI filter deteriorate its performances. In this paper, we propose to study a differential mode (DM) inductor in planar technology. The goal is to reduce the parasitic capacitance of the planar DM inductor via an improved parasitic capacitance cancellation technique. The technique is based on the results of an analytical method using Electric Field Decomposition and energy based approach. The cancellation is then realized through the structural parasitic capacitances under an optimal geometry configuration. The efficiency of the proposed cancellation technique is validated by measurements.

A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications

Abstract: An on-chip CMOS RF power detector (PD) is described that has internal temperature compensation and the highest reported linearity. The PD generates a DC current that is proportional to the square root of the RF input power by use of a new detection technique that utilizes p-n junction diodes. The generated DC current obtained by subtracting a replicated current produces the real-time temperature compensation. This subtraction method also suppresses the generated-current error caused by the parasitic element, thereby improving the linearity of the PD. The proposed on-chip PD was fabricated in 90-nm CMOS technology and integrated with a power amplifier (PA). The measured input range for a linearity error within ±0.5 dB was 27 dB at 0.824 GHz and 23 dB at 1.98 GHz. The measured results showed that the PD overcomes real-time temperature changes caused by self-heating, which depends on the output power of the PA. The PD consumes 0.3 mW at 0-dBm input power and occupies 0.04 mm2, which are small enough for the PA.

Planar inverted-F antenna with J-shaped slot and parasitic element for ultra-wide band application

Abstract: This paper presents a planar inverted-F antenna (PIFA) for ultra-wide band (UWB) communication, which is printed on a dielectric substrate of FR4-epoxy with 4.4 relative permittivity (ɛr), 2 mm thickness. This antenna is designed to be used in a 2.9–10.7 GHz frequency band, and a very wide bandwidth is realized by the addition of a parasitic element and a J-shaped slot to the PIFA. The effects of varying the parameters of the antenna on the performance have been investigated.

A comprehensive analysis of failure mechanisms: Latch up and second breakdown in IGBT(IXYS) and improvement

Abstract: The importance of the Insulate Gate Bipolar Transistor reliability has significantly increased due to the widespread use and target application of these devices which includes power conversion and motor drives. The IGBT as an optimal candidate as a power switch for applications requires high current, high voltage and high temperature operation [1], Nevertheless, one of the most important drawbacks of IGBTs is the latch up to the inherent parasitic thyristor structure, which leads to the gate control loss of the collector current and failure caused by second breakdown. The aim of this paper is to study the latch up performance at high operating temperature and to give a short discussion of the second breakdown phenomena during turn off process under disadvantageous conditions of IGBT for IXYS constructor. The circuit used in our study takes into account the effect of elements such as wires, inherent parasitic inductance of resistive elements and packaging. This analysis can help in understanding the operation mechanism with in the device during this condition. This is very helpful in developing optimum device. The need for a good physics based simulator (Spice) to carry out a reliability study is pointed out in this paper. The improvement of the electrical characteristics has been corroborated by focusing the analysis on the dynamic latch up and second breakdown phenomena. Furthermore, our reliability study permits us to improve the implantation of the device in a circuit, as well as its use in industrial operating conditions. Our simulation results indicate a decrease in the latching current density of the IGBT with an increase in the ambient temperature. Transient's characteristics show a decrease in maximum controllable current and an increase in the turnoff time.

Enhancement of FinFET performance using 25-nm-thin sidewall spacer grown by atomic layer deposition

Abstract: We report on performance enhancement of FinFETs with a 25-nm-short extension of the source/drain by using atomic layer deposition (ALD) of SiO 2 thin films for the side-wall spacer (SWS) of the gate electrode. Recently, the higher parasitic resistance ( R para ) of the source/drain region due to the narrow fin width is one of the issues to be solved for the FinFET devices. In this study, the performance of the FinFETs has been successfully improved by the reduction of the parasitic resistance using the ALD-SWS.

FinFET parasitic resistance reduction by segregating shallow Sb, Ge and As implants at the silicide interface

Abstract: This paper reports a new contact technology comprising antimony (Sb) co-implantation and segregation to reduce Schottky barrier height (SBH) and parasitic series resistance for N-FinFETs Experiments with shallow Sb, Ge and As co-implantation in the source/drain (S/D) regions of SOI FinFET found that all three implant species significantly reduced extrinsic resistance The Sb implant with a 5e13 cm−2 dose produced the best result with a 31% reduction of extrinsic resistance and a corresponding I on increase of 19% This optimum Sb implant is shown to reduce specific contact resistivity (ρ c ) below 10−8Ω-cm2 by decreasing the SBH and increasing the barrier steepness Electrostatic control comparable to the reference device indicates no degradation in short channel effects for either Sb, Ge or As This low ρ c is promising to address key FinFET scaling issues associated with parasitic series resistance for the 14nm node and beyond

3G (third-generation) antenna of full-screen intelligent mobile phone and design method of 3G antenna

Abstract: The invention relates to a design method of a 3G (third-generation) antenna of a full-screen intelligent mobile phone and the corresponding antenna. The design method comprises the steps of arranging a high-frequency circuit and a low-frequency circuit of the antenna on a circuit board, wherein the high-frequency circuit and the low-frequency circuit are isolated through an isolating trough, and adjusting the length and the width of the isolating trough to control resonance between the high-frequency circuit and the low-frequency circuit; and arranging a feed point and a ground point, wherein the ground point is arranged on the external side of the feed point, i.e. close to the side of the circuit board; and after an arranged second isolating trough leads out high-frequency second resonance, adjusting the length or the thickness of the second isolating trough to adjust the low-frequency band of the antenna, so as to match with a radio-frequency power amplifier to realize high frequency and high sensitivity. The antenna designed by adopting the design method provided by the invention has the advantages that the volume is small, the performance is excellent and the problem that the low-frequency radiation power and the low-frequency receiving sensitivity of the antenna are decreased because a method of adding a parasitic element to increase bandwidth is adopted can be effectively avoided.

Electrical properties of dielectric foil for embedded PCB capacitors

Abstract: One of the methods of achieving high packaging density of passive elements on the PCB is using the capacitors embedded in multilayer PCB. Test structures consisting of embedded capacitors were fabricated using the FaradFlex® capacitive internal layers. Impedance spectroscopy and equivalent circuit modelling was used to determine their electrical properties such as the capacitance, parasitic resistance and inductance. The use of several stages of accelerated ageing allowed us to test the durability of the structures. The results showed good quality stability of the embedded elements. The spatial distribution of the capacitance of the test structures on the surface of the PCB form was tested. The influence of the process parameters during lamination on the values of embedded capacitors was revealed.