Showing papers on "Parasitic element published in 2017"

A Multiloop Method for Minimization of Parasitic Inductance in GaN-Based High-Frequency DC–DC Converter

Abstract: Gallium nitride high electron mobility transistors (GaN HEMTs) are promising switching devices in high-efficiency and high-density dc–dc converters due to their fast switching speed and small conduction resistance. However, GaN HEMTs are very sensitive to parasitic inductance because of their high switching speed, low-threshold voltage, and small driving safety margin. Parasitic inductance can cause severe voltage overshoot and ringing, which may result in electromagnetic interference issues, false turn-on, or even device breakdown. This paper aims at reducing the parasitic inductance (including power loop inductance and driver loop inductance) by optimizing the layout. First, a multiloop method is proposed to reduce the parasitic inductance. Optimization of both the conventional single-loop structure and the proposed multiloop structure are presented. Second, three kinds of power loop layouts based on the proposed multiloop structure are realized on PCB substrate and one of them is realized on aluminum nitride (AlN) substrate, which has higher thermal conductivity but less copper layers. The power loop inductance on PCB substrate is reduced to 0.1 nH, which is only 25% of the state-of-art layout. The power loop inductance on AlN substrate is reduced to 0.22 nH. Third, the driver loop layout is optimized and achieves 50% reduction of driver loop inductance compared with the conventional single-layer layout. Finally, integrated modules using the proposed layouts are built to validate the analyses and designs.

Parasitic Inductance and Capacitance-Assisted Active Gate Driving Technique to Minimize Switching Loss of SiC MOSFET

Abstract: High di/dt and dv/dt of SiC MOSFET cause a considerable amount of overshoot in device voltage and current during switching transients in the presence of inverter layout parasitic inductance and load parasitic capacitance. The excessive overshoots in device voltage and current cause failure of the device. Moreover, these uncontrolled overshoots increase the switching loss in the inverter. It is difficult to reduce parasitic inductance beyond a certain point. This paper proposes an active gate driving technique, which allows inverter to operate with moderate amount of layout parasitic inductance and load parasitic capacitance. The proposed technique dramatically reduces switching loss of the SiC MOSFET with the help of existing parasitic elements. The proposed switching loss reduction technique is termed as quasi zero switching . The developed active gate driver has been tested in a double pulse test setup and a 10 kW two-level voltage source inverter driving an induction motor.

200 V Enhancement-Mode p-GaN HEMTs Fabricated on 200 mm GaN-on-SOI With Trench Isolation for Monolithic Integration

Abstract: Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate In this letter, we propose to use GaN-on-SOI (silicon-on-insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO2 buried layer By well-controlled epitaxy and device fabrication, high-performance 200 V enhancement-mode (e-mode) p-GaN high electron mobility transistors with a gate width of 36 mm are achieved This letter demonstrates that by using GaN-on-SOI in combination with trench isolation, it is very promising to monolithically integrate GaN power systems on the same wafer to reduce the parasitic inductance and die size

On Developing One-Chip Integration of 1.2 kV SiC MOSFET and JBS Diode (JBSFET)

Abstract: This paper presents the design, fabrication, and characterization of the SiC JBSFET (junction barrier Schottky (JBS) diode integrated MOSFET). The fabrication of the JBSFET adopted a novel single metal, single thermal treatment process to simultaneously form ohmic contacts on n+, p+ implanted regions, and Schottky contact on the n-4H-SiC epilayer. The presented SiC JBSFET uses 40% smaller wafer area because the diode and MOSFET share the edge termination as well as the current conducting drift region. The proposed single chip solution of MOSFET/JBS diode functionalities eliminates the parasitic inductance between separately packaged devices allowing a higher frequency operation in a power converter.

Design of a low parasitic inductance SiC power module with double-sided cooling

Abstract: In this paper, a low parasitic inductance SiC power module with double-sided cooling is designed and compared with a baseline double-sided cooled module With the unique 3D layout utilizing vertical interconnection, the power loop inductance is effectively reduced without sacrificing the thermal performance Both simulations and experiments are carried out to validate the design Q3D simulation results show a power loop inductance of 163 nH, verified by the experiment, indicating more than 60% reduction of power loop inductance compared with the baseline module With 0Ω external gate resistance turn-off at 600V, the voltage overshoot is less than 9% of the bus voltage at a load of 446A

Steerable Higher Order Mode Dielectric Resonator Antenna With Parasitic Elements for 5G Applications

Abstract: This paper presents the findings of a steerable higher order mode (TE $^{\mathrm {y}}_{1\delta 3}$ ) dielectric resonator antenna with parasitic elements. The beam steering was successfully achieved by switching the termination capacitor on the parasitic element. In this light, all of the dielectric resonator antennas (DRAs) have the same dielectric permittivity similar to that of ten and excited by a $50\Omega $ microstrip with a narrow aperture. The effect of the mutual coupling on the radiation pattern and the reflection coefficient, as well as the array factor, was investigated clearly using MATLAB version 2014b and ANSYS HFSS version 16. As the result, the antenna beam of the proposed DRA array managed to steer from −32° to +32° at 15 GHz. Furthermore, the measured antenna array showed the maximum gain of 9.25 dBi and the reflection coefficients which are less than −10 dB with the bandwidth more than 1.3 GHz, which is viewed as desirable for device-to-device communication in 5G Internet of Things applications.

Experimental Extraction of Parasitic Capacitances for High-Frequency Transformers

Abstract: Parasitic capacitances of the high-frequency (HF) transformer used in dc–dc converter impact harmonic analysis of the transformer and interactions with the converter. Resonant frequencies of open- and short-circuit impedances characteristics (ICs) have been widely used to extract parasitic capacitances of HF transformers, but it was reported that some resonant frequencies were unobtainable as they were too high where the ICs fluctuated heavily, and parasitic capacitances remained unevaluated. In this paper, resonance features of ICs and voltage transfer characteristics (TCs) are investigated, and a new frequency of voltage TC is used for extracting parasitic capacitances. By analyzing inner links of known impedance resonant frequencies, why and which resonant frequencies are likely to be unobtainable is revealed. Furthermore, a new frequency corresponding to zero of TC, accounting for parallel resonance between leakage inductance and mutual capacitance of the two windings, is used to extract parasitic capacitances. With this new frequency mutual capacitance of the windings is evaluated, and missing equation due to unobtainable impedance resonant frequency is added. Besides, merits and limitations of extracting parasitic capacitances based on ICs and TCs are analyzed. These techniques are verified with several HF transformer prototypes in the laboratory.

Online Inductor Parameters Identification by Small-Signal Injection for Sensorless Predictive Current Controlled Boost Converter

Abstract: In a sensorless predictive current controlled boost converter, parameterizing the inductor plays an important role in controller performance. In this paper, a solution for inductor parameters online identification is investigated. A small-signal injection strategy is proposed to create a transient state, and convergence problem of inductance identification in steady state can be avoided. Then, a charge balance current observer (CBCO), derived from capacitor current charging balance concept, is adopted to estimate the inductor current for inductance identification. Since inductance is not used in CBCO, current estimation is not affected by inductance identification error. Because of rank-deficient problem, instead of identifying inductor parasitic resistance solely, the inductor equivalent parasitic resistance is derived. By applying it into the conventional current observer for current control loop, the accuracy of current estimation can still be guaranteed since more parasitic effects are included. To improve the accuracy of inductance identification, a load identification method is investigated. Furthermore, the effect of the equivalent series resistance of output capacitor on the proposed algorithm is analyzed. Finally, its effectiveness is verified by experimental results.

Fabrication of Vacuum-Sealed Capacitive Micromachined Ultrasonic Transducers With Through-Glass-Via Interconnects Using Anodic Bonding

Abstract: This paper presents a novel fabrication method for vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT) arrays that are amenable to 3D integration. This paper demonstrates that MEMS structures can be directly built on a glass substrate with preformed through-glass-via (TGV) interconnects. The key feature of this new approach is the combination of copper through-glass interconnects with a vibrating silicon-plate structure suspended over a vacuum-sealed cavity by using anodic bonding. This method simplifies the overall fabrication process for CMUTs with through-wafer interconnects by eliminating the need for an insulating lining for vias or isolation trenches that are often employed for implementing through-wafer interconnects in silicon. Anodic bonding is a low-temperature bonding technique that tolerates high surface roughness. Fabrication of CMUTs on a glass substrate and use of copper-filled vias as interconnects reduce the parasitic interconnect capacitance and resistance, and improve device performance and reliability. A 16×16-element 2D CMUT array has been successfully fabricated. The fabricated device performs as the finite-element and equivalent circuit models predict. A TGV interconnect shows a 2-Ω parasitic resistance and a 20-fF shunt parasitic capacitance for 250-μm via pitch. A critical achievement presented in this paper is the sealing of the CMUT cavities in vacuum using a PECVD silicon nitride layer. By mechanically isolating the via structure from the active cells, vacuum sealing can be ensured even when hermetic sealing of the via is compromised. Vacuum sealing is confirmed by measuring the deflection of the edge-clamped thin plate of a CMUT cell under atmospheric pressure. The resonance frequency of an 8-cell 2D array element with 78-μm diameter circular cells and a 1.5-μm plate thickness is measured as 3.32 MHz at 15-V dc voltage (80% V pull-in ). [2016-0200].

On the Effect of Disorder on Stray Capacitance of Transformer Winding in High-Voltage Power Supplies

Abstract: Stray capacitance of transformer winding is an important parasitic element influencing the behavior of the switching power converters, especially for high-voltage transformers. There are various methods for calculating the stray capacitance in transformers and inductors with ordered windings. However, an ordered winding is less likely with an increased number of turns and layers. In this paper, it is shown that a slight disorderliness in winding leads to a considerable difference between the value of winding stray capacitance of the former ordered winding and its slightly disordered scheme. Therefore, regular methods for calculating the stray capacitance have significant errors in a disordered winding. A generic method is proposed to calculate the stray capacitance of a winding with disordered turns. The proposed method is to apply the probabilistic tools to evaluate the possible position of winding turns and calculation of stray capacitance for all possible winding diagrams. As the number of possible winding diagrams is very large, especially in high turn windings, Kolmogorov–Smirnov theorem is used to estimate the winding stray capacitance based on the reduced number of possible winding diagrams. The energy method is used to calculate the equivalent stray capacitance of winding. Using this calculation method, the effect of disorder and some other parameters on the value of stray capacitance is investigated. The proposed method is tested and validated with the computer simulation and the experimental measurement.

Flexible epoxy-resin substrate based 1.2 kV SiC half bridge module with ultra-low parasitics and high functionality

Abstract: To take full advantages of Wide Bandgap power semiconductor devices, breakthroughs on power module development are heavily explored nowadays. This paper introduces a 1.2kV SiC half bridge intelligent power module utilizing 80μm flexible epoxy-resin as substrates instead of traditional Direct-bonded Copper, for better thermal-stress management and lower cost. The investigation on the flexible epoxy-resin material indicates that it has low leakage current even at 250 °C, and high thermal conductivity up to 8 W/mK. No bonding wires are applied in the half bridge power module, instead, double-side solderable SiC MOSFET and diodes are fabricated and utilized for low parasitics and double-side cooling function. To further decrease the entire parasitic inductance on the power loop, a “Stack Structure” is proposed in this work to vertically connect highside and lowside switches with lower interconnection path than traditional power module technology. Simulation indicates that the parasitic inductance on the power loop is less than 1.5 nH. More functionality is achieved by integrating the main power stage with gate driver circuits. Digital isolations are also included in the half bridge module, together with a Low Dropout regulator to eliminate the numbers of auxiliary power supply required by the power module. The size of the entire module is about 35mm × 15mm ×7mm. Electrical simulations and measurements, including leakage current, parasitic extractions, device characteristics, verified that the designed module can work properly with no degradation on the SiC devices, with 12ns turn-off and 48ns turn-on at 800V bus voltage, and 0.63 mJ, 0.23 mJ as turn-on and turn-off loss, respectively.

Optimization of the balance between the gate-drain capacitance and the common source inductance for preventing the oscillatory false triggering of fast switching GaN-FETs

Abstract: GaN-FETs are attractive switching devices for their fast switching capability. However, they often suffer from the oscillatory false triggering, i.e. a series of self-sustaining repetitive false triggering induced after a fast switching. The purpose of this paper is to derive a design instruction to prevent this phenomenon. According to the previous study, the oscillatory false triggering was found to be caused by a parasitic oscillator circuit formed of a GaN-FET, its parasitic capacitance, and the parasitic inductance of the wiring. This paper analyzed the oscillatory condition to elucidate the design requirement to prevent the oscillatory false triggering. As a result, balancing the gate-drain parasitic capacitance and the common source inductance to achieve an appropriate ratio was found to be essential for preventing the oscillatory false triggering. Experiment successfully supported prevention of this phenomenon by balancing these two factors.

An improved SiC MOSFET-gate driver integrated power module with ultra low stray inductances

Abstract: An improved SiC MOSFET-gate driver integrated half-bridge module with folded layout using direct bonded copper (DBC) substrate is designed, fabricated, and tested. The bottom layer of the DBC is used as part of the power loop to achieve major reduction in the loop stray inductance. Due to the low parasitic inductance and capacitance, the gate resistor is chosen as zero to reduce the switching loss and the EMI performance is improved under high switching speed. Simulation and experimental results show the better switching performance comparing with traditional one-layer module.

Analytical investigation on design instruction to avoid oscillatory false triggering of fast switching SiC-MOSFETs

Abstract: SiC-MOSFETs have attracting increasing attention because of their outstanding characteristics that contributes to high efficiency and high power density of power converters. However, compared to conventional Si-IGBTs, SiC-MOSFETs are susceptible to false triggering, because they tend to generate large switching noise due to ultrafast switching capability and have a lower threshold voltage in high temperature operation. Particularly, disastrous oscillation of repetitive false triggering can occur after a fast turn-off, which is the severe issue for practical application of SiC-MOSFETs. The purpose of this paper is to give an instruction to avoid this phenomenon. This paper hypothesized that the repetitive false triggering is the parasitic oscillation caused by parasitic capacitance of SiC-MOSFET, and parasitic inductance of wiring. Based on this hypothesis, this paper analyzed the oscillatory condition of the parasitic oscillator to propose a design instruction to avoid the oscillatory false triggering. The result revealed that the parasitic inductance of the gate, drain, and source wiring should be designed so that the resonance frequency of the parasitic LC resonator in the gating circuit is far apart from that of the power circuit. This paper also presents experimental results that support appropriateness of the proposed design instruction.

A novel low inductive 3D SiC power module based on hybrid packaging and integration method

Abstract: This paper presents a 1200 V, 120 A SiC phase-leg power module built in a novel low inductive 3D hybrid structure. The power module consists of DBC substrate and Flexible Printed Circuit (FPC) board equipped with SiC MOSFETs and diodes. The parasitic inductance of the power module is significantly minimized by using the FPC board and the proper layout design to 0.79 nH (extracted by Q3D). The power terminals are directly extended from the FPC board with only 0.85 nH stray inductance, and the DC decoupling capacitors are integrated in the module to decrease the peak turn-off voltage. The parasitic inductance of the module is verified by Impedance Analyzer measurement. Meanwhile, the double pulse test results show the switching speed of the FPC module is 1.6 times faster and has only half the overshoot voltage when compared with the commercial module. By integrating gate drivers, DC-link, and heatsink, the designed full SiC phase-leg 3D module has the potential to improve the power density.

Multiband split-ring resonator based planar inverted-F antenna for 5G applications

Abstract: 5G, the fifth generation of wireless communications, is focusing on multiple frequency bands, such as 6 GHz, 10 GHz, 15 GHz, 28 GHz, and 38 GHz, to achieve high data rates up to 10 Gbps or more. The industry demands multiband antennas to cover these distant frequency bands, which is a task much more challenging. In this paper, we have designed a novel multiband split-ring resonator (SRR) based planar inverted-F antenna (PIFA) for 5G applications. It is composed of a PIFA, an inverted-L parasitic element, a rectangular shaped parasitic element, and a split-ring resonator (SRR) etched on the top plate of the PIFA. The basic PIFA structure resonates at 6 GHz. An addition of a rectangular shaped parasitic element produces a resonance at 15 GHz. The introduction of a split-ring resonator produces a band notch at 8 GHz, and a resonance at 10 GHz, while the insertion of an inverted-L shaped parasitic element further enhances the impedance bandwidth in the 10 GHz band. The frequency bands covered, each with more than 1 GHz impedance bandwidth, are 6 GHz (5–7 GHz), 10 GHz (9–10.8 GHz), and 15 GHz (14-15 GHz), expected for inclusion in next-generation wireless communications, that is, 5G. The design is simulated using Ansys Electromagnetic Suite 17 simulation software package. The simulated and the measured results are compared and analyzed which are generally in good agreement.

Design of a novel, high-density, high-speed 10 kV SiC MOSFET module

Abstract: High-density packaging of fast-switching power semiconductors typically requires low thermal resistance and parasitic inductance. High-density packaging of high-voltage semiconductors, such as 10 kV SiC MOSFETs, has the added challenge of maintaining low electric field concentration in order to prevent premature dielectric breakdown. This work proposes a wire-bond-less, sandwich structure with embedded decoupling capacitors and stacked ceramic substrates in order to realize a high-density module capable of high-speed switching with low electric field concentration and EMI. This is the first time that these advanced packaging techniques have been applied to a 10 kV SiC MOSFET module.

High Performance Chip-Partitioned Millimeter Wave Passive Devices on Smooth and Fine Pitch InFO RDL

Abstract: High performance millimeter wave passive devices are realized on smooth, fine pitch InFO redistribution layer (RDL). These passive devices are balun, power combiner, coupler, and microstrip line and the electrical performances are measured from 0.1GHz to 67 GHz through VNA. The measurement results show that the transmission loss of on-InFO balun (4.3 dB), the power divider (4.3 dB), and the coupler (4.9 dB) outperforms on-chip one by 2.1 dB, 1 dB, and 0.2 dB, respectively. While the transmission loss of microstrip line (0.34 dB/mm) is better than on-chip one by 0.17 dB/mm at 60 GHz. Furthermore, the parasitic of InFO chip-package interconnection has been investigated and compared to other technologies with and without solder bumps. The parasitic resistance, inductance, and capacitance for InFO interconnection are 75 %, 76 %, and 14 % lower than those for chip-last, face-down technology. Parasitic resistance for InFO RDL is 10 % lower than that for chip-first face-down technology with uneven RDL.

Design and development of a high-density, high-speed 10 kV SiC MOSFET module

Abstract: High-density packaging of fast-switching power semiconductors typically requires low parasitic inductance, high heat extraction, and high thermo-mechanical reliability. High-density packaging of high-voltage power semiconductors, such as 10 kV SiC MOSFETs, also requires low electric field concentration in order to prevent premature dielectric breakdown. Consequently, in addition to the usual electromagnetic, thermal, and mechanical analyses, the electric fields must also be evaluated. This is the first detailed report on the optimization of a high-voltage SiC MOSFET power module.

Compensating for Parasitic Voltage Drops in Resistive Memory Arrays

Abstract: Parasitic resistances cause devices in a resistive memory array to experience different read/write voltages depending on the device location, resulting in uneven writes and larger leakage currents. We present a new method to compensate for this by adding extra series resistance to the drivers to equalize the parasitic resistance seen by all the devices. This allows for uniform writes, enabling multi-level cells with greater numbers of distinguishable levels, and reduced write power, enabling larger arrays.

Paralleling 650 V/ 60 A GaN HEMTs for high power high efficiency applications

Abstract: In this paper, the design and operation of two 650 V/ 60 A Gallium Nitride (GaN) devices in parallel is discussed in detail, further, the challenges faced and the trade-offs required for paralleling high speed GaN devices are also examined. The dynamic characterization of two devices in parallel is presented in detail. The phase leg design requires both power loops and gate loops to be as small and as identical as possible for the two devices as for high speed GaN devices, even a small parasitic inductance or capacitance added due to the layout causes high overshoot in device voltage and current. The Double pulse tester (DPTer) design required for dynamic characterization of devices in parallel is slightly different from the phase leg design. Each device current is measured separately using a current shunt connected in series with the device. The shunts also add parasitic inductances in series with each device which limits the performance of the DPTer. Dynamic characterization performed includes characterization of a single device till 400 V, 60 A which then goes on to discuss characterization for paralleled devices. The major challenge faced in paralleling is the issue of circulating current between the two devices during turn-on transient which is discussed in detail, its causes and ways to mitigate the circulating current are also presented. This paper also examines two designs-the first one is the recommended design from GaN Systems[1] which uses the same split off-state and split on-state gate resistors, thus using only one resistor to control circulating current, turn-off speed and the Miller effect. The second design presented is the improved version of the recommended design which has completely different split on-state and split off-state gate resistors, thus using different gate resistors to control circulating current and turn-off speed. The performance of both the designs is compared from Double Pulse Test (DPT) results.

Performance of a 1.2kV, 288A full-SiC MOSFET module based on low inductance packaging layout

Abstract: This paper presents a novel designed SiC MOSFET module based on low-inductance layout using split damping capacitors The voltage rating of this power module is 1200V and the current rating is 288A The influence of parasitic inductance on SiC MOSFET in one-phase-leg module is analyzed, and the design of the SiC MOSFET module is also described in this work The double pulse test is used to evaluate and compare the characteristics of proposed SiC MOSFET module with a 1200V, 300A commercial SiC MOSFET The overshoot voltage at 600V, 110A during turn-off transient of proposed SiC MOSFET module is smaller than the commercial SiC MOSFET, which means lower parasitic inductance for SiC MOSFET module The voltage spike of such SiC module remains insensitive to variation of temperature when tested up to the baseplate temperature of 100 0C

Loss analysis for efficiency improvement of the integrated buck-flyback converter for LED driving applications

Abstract: In this paper, a study of the losses in the integrated buck-flyback converter (IBFC) used as high-power-factor LED driver is presented. The final goal of this study is to investigate the possibilities of increasing the efficiency of this converter, which is usually in the range of 85–89%. The procedure of the improvement is done by obtaining the equations for the value of the current through each component in terms of the converter parameters. With these equations the converter can be redesigned in order to increase the efficiency. The value of the current is found in average value, or root mean square (RMS) value depending on the type of the parasitic element, whether it is modeled by a parasitic forward voltage source or by a parasitic resistance, respectively. The equations found are proved mathematically and verified by simulation. A chart for the losses in each part is illustrated using the proved formulas and the parasitic model of each element and verified from the designed IBFC prototype. The presented methodology can easily be applied to other integrated converters. Finally, the paper presents some ideas to increase the eificiency of the IBFC.

Effects of parasitic inductance on performance of 600-V GaN devices

Abstract: This paper presents a comparison of two identical gallium nitride (GaN) cascode transistors with different TO-220 packaging configurations. The transistors were analyzed using a precision frequency domain impedance analyzer; and lumped, per-terminal estimates were developed for the parasitic package inductance of each device. It was found that the devices have different per-terminal lead inductances, despite the fact that the dies are manufactured using similar processes. To assess the impact of the different package configurations, the devices were subjected to double pulse tests (DPT), and switching loss measurements were taken. The devices were also modeled using SaberRD (Synopsys) and simulated in the same DPT experimentally implemented. The results show good agreement between the models' predicted behavior and measured behavior. These validated models can be used to further predict the impact of each parasitic inductance on the device's transient performance. This is particularly essential for GaN-based power electronics, where the parasitic inductance can significantly affect device performance and reliability.

Investigation of the effects of load parasitic inductance on SiC MOSFETs switching performance

Abstract: Parasitic inductances are responsible for oscillations and overshoots in the switching waveforms of SiC MOSFETs under high-frequency operations. In addition to the parasitic inductance of PCB board, bus-bar, device packaging, and drive circuit, the load inductance used for energy storage represents another source of parasitic inductance in SiC MOSFETs converters. Therefore, it is necessary to study the effect of the parasitic inductance contributed by inductive loads. This paper studies the effects of the load parasitic inductance on the switching performance of a SiC MOSFET-based switching power pole (SPP) or what traditionally defined as a half-bridge. The goal is to identify the influence of the load parasitic inductance on the overshoot and ringing in the waveforms of the device drain-to-source voltage and drain current. Using a simple procedure based on experimental measurements of the device drain-to-source voltage and drain current along with the mathematical formula of the inductance, the value of the parasitic inductance of the load inductor was evaluated.

Modeling of FinFET Parasitic Source/Drain Resistance With Polygonal Epitaxy

Abstract: In this paper, we introduce a new compact model of the parasitic resistance of a FinFET with a hexagonal-shaped raised source–drain (S/D) structure. In contrast to previous models that divided the extrinsic S/D region into three parts, we redefined the region boundaries and modeled them as a series connection of accumulation resistance, gradient resistance, bulk resistance, and contact resistance. The newly added bulk resistance model accounts for the highly doped silicon region. We also significantly improved the contact resistance model to reflect the contact area and contact resistivity for better accuracy in the raised S/D region. We validated the accuracy of our model by varying the gate voltage, doping diffusion length, epitaxy silicon height, and contact resistivity, finding the model errors to be within 2% of the 3-D technology CAD device simulation results.

A 28 GHz Rectangular Patch Antenna with Parasitic Element for Small Satellite Applications

Abstract: This paper introduces a Ka band antenna candidate for small satellite communications. The design is a compact rectangular patch antenna with inset feed and parasitic element. The antenna's performances are analyzed using both HFSS 15.0 and CST Microwave Studio 2017 simulators. The designed antenna provides a high gain, better efficiency, ultra-wide band (UWB), and a unidirectional radiation pattern. The geometry and size of the parasitic element and distance between it and the patch are optimized to achieve the desired results.

A study on parasitic inductance reduction design in GaN-based power converter for high-frequency switching operation

Abstract: This report studies the influence of printed circuit board (PCB) design on voltage overshoot and ringing oscillation in switching operation of gallium nitride gate injection transistor (GaN-GIT) for high-frequency DC-DC converter. The parasitic inductances in the main power loop have been identified based on moment of method (MoM) analysis and frequency characteristics of impedance measured with 2-port shunt-thru method. The measured switching characteristics of GaN-GIT in a 5 MHz DC-DC boost converter shows that a small-ESL ceramic capacitor connected across the DC-link can reduce the effective power loop inductances and can improve both voltage overshoot and the damping of ringing oscillation.