Showing papers on "Ripple published in 2013"

Dual active bridge based battery charger for plug-in hybrid electric vehicle with charging current containing low frequency ripple

Abstract: High power density is strongly preferable for the on-board battery charger of Plug-in Hybrid Electric Vehicle (PHEV). Wide band gap devices, such as Gallium Nitride HEMTs are being explored to push to higher switching frequency and reduce passive component size. In this case, the bulk DC link capacitor of AC-DC Power Factor Correction (PFC) stage, which is usually necessary to store ripple power of two times the line frequency in a DC current charging system, becomes a major barrier on power density. If low frequency ripple is allowed in the battery, the DC link capacitance can be significantly reduced. This paper focuses on the operation of a battery charging system, which is comprised of one Full Bridge (FB) AC-DC stage and one Dual Active Bridge (DAB) DC-DC stage, with charging current containing low frequency ripple at two times line frequency, designated as sinusoidal charging. DAB operation under sinusoidal charging is investigated. Two types of control schemes are proposed and implemented in an experimental prototype. It is proved that closed loop current control is the better. Full system test including both FB AC-DC stage and DAB DC-DC stage verified the concept of sinusoidal charging, which may lead to potentially very high power density battery charger for PHEV.

Active Power Decoupling for High-Power Single-Phase PWM Rectifiers

Abstract: Single-phase pulsewidth modulation rectifiers suffer from ripple power pulsating at twice the line frequency. The ripple power is usually filtered by a bulky capacitor bank or an LC branch, resulting in lower power density. The alternative way is active power decoupling, which uses an active circuit to direct the pulsating power into another energy-storage component. The main dc-link filter capacitor can, therefore, be reduced substantially. This paper proposed a new scheme of active power decoupling. The circuit consists of a third leg, an energy-storage capacitor and a smoothing inductor. The topology combined the advantages of high energy-storage efficiency and low requirement on control bandwidth. Both the pulsating power from the ac source and the reactive power of the smoothing inductors are taken into consideration when deriving the power decoupling scheme. The active power filter's (APF) capacitor voltage control system consists of inner loop pole-placement control and outer loop proportional-resonant control. To enhance the steady-state performance, the capacitor voltage reference is modified in a closed-loop manner. Simulation and experimental results show that the proposed APF scheme has good power decoupling performance and is more suited for high-power applications where switching frequency is limited.

A Cascade MPC Control Structure for a PMSM With Speed Ripple Minimization

Abstract: This paper addresses the problem of reducing the impact of periodic disturbances arising from the current sensor offset error on the speed control of a permanent-magnet synchronous motor. The new results are based on a cascade model predictive control scheme with an embedded disturbance model. Supporting experimental results, where the per-unit model is used to improve numerical conditioning, are also given.

Mitigation of Low-Frequency Current Ripple in Fuel-Cell Inverter Systems Through Waveform Control

Abstract: Fuel-cell power systems comprising single-phase dc/ac inverters draw low-frequency ac ripple currents at twice the output frequency from the fuel cell. Such a 100/120 Hz ripple current may create instability in the fuel-cell system, lower its efficiency, and shorten the lifetime of a fuel cell stack. This paper presents a waveform control method that can mitigate such a low-frequency ripple current being drawn from the fuel cell while the fuel-cell system delivers ac power to the load through a differential inverter. This is possible because with the proposed solution, the pulsation component (cause of ac ripple current) of the output ac power will be supplied mainly by the two output capacitors of the differential inverter while the average dc output power is supplied by the fuel cell. Theoretical analysis, simulation, and experimental results are provided to explain the operation and showcase the performance of the approach. Results validate that the proposed solution can achieve significant mitigation of the current ripple as well as high-quality output voltage without extra hardware. Application of the solution is targeted at systems where current ripple mitigation is required, such as for the purpose of eliminating electrolytic capacitor in photovoltaic and LED systems.

A High Power Density Single Phase Pwm Rectifier with Active Ripple Energy Storage

Abstract: It is well known that there exist second-order harmonic current and corresponding ripple voltage on dc bus for single phase PWM rectifiers The low frequency harmonic current is normally filtered using a bulk capacitor in the bus which results in low power density? This project proposed an active ripple energy storage method that can effectively reduce the energy storage capacitance The feed- forward control method and design considerations are provided

Variable Switching Frequency PWM for Three-Phase Converters Based on Current Ripple Prediction

Abstract: Compared with the widely used constant switching frequency pulse-width-modulation (PWM) method, variable switching frequency PWM can benefit more because of the extra freedom Based on the analytical expression of current ripple of three-phase converters, variable switching frequency control methods are proposed to satisfy different ripple requirements Switching cycle $T_{s}$ is updated in DSP in every interruption period based on the ripple requirement Two methods are discussed in this paper The first method is designed to arrange the current ripple peak value within a certain value and can reduce the equivalent switching frequency and electromagnetic interference (EMI) noise; the second method is designed to keep ripple current RMS value constant and reduce the EMI noise Simulation and experimental results show that variable switching frequency control could improve the performance of EMI and efficiency without impairing the power quality

Ultra-High-Contrast and Tunable-Bandwidth Filter Using Cascaded High-Order Silicon Microring Filters

Abstract: High-contrast optical filtering is demonstrated using cascaded silicon microrings. We report an experimental measurement of a record 100 dB pass-band to stop-band contrast, tunable 12–125 GHz passband full-width at half-maximum, band-center insertion loss ripple ${ , and a group delay ripple ${ , using transverse electric polarized light.

Optimal injection of harmonics in circulating currents of modular multilevel converters for capacitor voltage ripple minimization

Abstract: This paper proposes an algorithm to calculate the optimal amplitude and phase of the harmonic current components that can be injected in the circulating currents of a modular multilevel converter (MMC) to minimize the capacitor voltage fluctuations. An optimal second harmonic component and an optimal set of second and fourth harmonic components are proposed. Simulation results are obtained in MATLAB/Simulink environment to study the effectiveness of the calculated optimal currents. Selected experimental results have been obtained from an MMC laboratory prototype, testing the effects of the circulating currents. The reported results demonstrate the effectiveness of using a fourth harmonic component in the circulating current, which improves the effect of the second harmonic on reducing the capacitor voltage fluctuations.

Unified Active Filter and Energy Storage System for an MW Electric Vehicle Charging Station

Abstract: A network of fast-charging stations is of great importance for widespread adoption of electric vehicles (EV) if the so-called range anxiety issue is to be resolved. As with petrol stations, we expect that multiple chargers will be co-located to form charging stations. This layout allows for the fast-charging station to make use of a common rectifier stage and several dc/dc stages to charge multiple EVs. This paper builds on our previous work where we proposed a novel dc-side filter for the 12-pulse rectifier and investigated the power profile for a MW fast-charging station. In this paper, we propose a novel control approach for the filter, based on the virtual resistor injection, which results in further reduction in dc ripple, ac-side harmonics, and filter VA ratings. We also demonstrate that, with the proposed topology and control, the filter stage can be used as dc-side energy storage system.

Optimization of Switching Losses and Capacitor Voltage Ripple Using Model Predictive Control of a Cascaded H-Bridge Multilevel StatCom

Abstract: This paper further develops a model predictive control (MPC) scheme which is able to exploit the large number of redundant switching states available in a multilevel H-bridge StatCom (H-StatCom). The new sections of the scheme provide optimized methods to tradeoff the harmonic performance with converter switching losses and capacitor voltage ripple. Varying the pulse placement within the modulation scheme and modifying the heuristic model of the voltage balancing characteristics allows the MPC scheme to achieve superior performance to that of the industry standard phase shifted carrier modulation technique. The effects of capacitor voltage ripple on the lifetime of the capacitors are also investigated. It is shown that the MPC scheme can reduce capacitor voltage ripple and increase capacitor lifetime. Simulation and experimental results are presented that confirm the correct operation of the control and modulation strategies.

Decrease in Photovoltaic Power Output from Ripple: Simple General Calculation and the Effect of Partial Shading

Abstract: The effect of voltage ripple on the power output of a photovoltaic panel is calculated and tested experimentally. Voltage ripple induces a much larger power reduction than would be predicted from a conventional small-signal model of the panel's I-V characteristic, even with small ripple amplitude. A simple expression is provided to calculate power reduction from rms ripple voltage, for any ripple waveform shape. The effect of ripple on power output can be much more severe under nonuniform irradiance as can result from partial shading. The results are important for 1) consideration of double-line-frequency ripple in single-phase inverters; 2) high-frequency switching ripple with any power converter in a photovoltaic system; and 3) perturbations and tracking errors in maximum-power-point tracking systems.

Predictive sorting algorithm for modular multilevel converters minimizing the spread in the submodule capacitor voltages

Abstract: The modular multilevel converter is a suitable topology for bidirectional ac-dc conversion in high-voltage high-power applications. By connecting submodule circuits in series, a high-voltage waveform with excellent harmonic performance can be achieved with a very high efficiency and low switching frequency. The balancing of the capacitor voltages will, however, become increasingly difficult as the switching frequency is reduced. Although the capacitor voltages can be kept balanced over time even at the fundamental switching frequency, the spread and thus also the peak variation in the capacitor voltages will typically increase at lower switching frequencies. This paper presents a capacitor voltage balancing strategy which aims to combine a low switching frequency with a low capacitor voltage ripple. This is done by a predictive algorithm that calculates the amount of charge that must be stored in the submodule capacitors during the following fundamental frequency period. The converter is then controlled in such a way that the stored charge in the submodule capacitors is evenly distributed among all the submodules when the capacitor voltages reach their maximum values. In this way, it is possible to limit the peak voltage in the capacitor at switching frequencies as low as 2-3 times the fundamental frequency. The capacitor voltage balancing strategy is first validated by simulation results at 110 Hz switching frequency. It is observed that when the proposed method is used, the capacitor voltage ripple is 35% lower compared to the case when a conventional sorting algorithm is used. The capacitor voltage balancing strategy is also validated experimentally at 130 Hz switching frequency. The experimental results show that it is possible to combine the proposed method with previously presented circulating-current control methods.

Discontinuous Decoupled PWMs for Reduced Current Ripple in a Dual Two-Level Inverter Fed Open-End Winding Induction Motor Drive

Abstract: This paper presents investigations on current ripple in a dual 2-level inverter feeding an open-end winding induction motor drive. Pulsewidth modulations (PWMs) for the independently controlled inverters are implemented using a simple effective time placement affected by offset-time concept, thus, eliminating the use of sector identification and lookup tables. Analytical expressions for ripple content in the motor phase current are developed and a current trajectory is theoretically obtained directly from the switching states of the dual inverter in a stationary reference frame. In addition, this paper also describes a current ripple trajectory in the motor by exploring the freedom of independently operating the individual inverters with different PWMs. Based on the analysis, discontinuous PWMs are employed for the individually inverters that not only offer the advantage of reducing the total switching commutations in the inverters but also reduces the current ripple. Analytical expression for the RMS ripple current and variation in RMS ripple current in one cycle of operation for different PWMs are also presented for the entire speed range of the dual-inverter drive. The performance of the dual-inverter drive with the proposed PWM variants is first studied analytically and then verified by performing suitable experiments on a 1-kW open-end winding induction motor drive.

Bridgeless SEPIC Converter With a Ripple-Free Input Current

Abstract: Conventional power factor correction (PFC) single-ended primary inductor converter (SEPIC) suffers from high conduction loss at the input bridge diode. To solve this problem, a bridgeless SEPIC converter with ripple-free input current is proposed. In the proposed converter, the input bridge diode is removed and the conduction loss is reduced. In addition, the input current ripple is significantly reduced by utilizing an additional winding of the input inductor and an auxiliary capacitor. Similar to the conventional PFC SEPIC converter, the input current in a switching period is proportional to the input voltage and near unity power is achieved. The operational principles, steady-state analysis, and design equations of the proposed converter are described in detail. Experimental results from a 130 W prototype at a constant switching frequency of 100 kHz are presented to verify the performance of the proposed converter.

Dynamic Modeling and Control for SPMSMs With Internal Turn Short Fault

Abstract: A dynamic model for a faulted surface-mount permanent magnet synchronous motor (SPMSM) is derived using a deformed flux model. In reflecting the internal turn short into the dynamics, the variations in inductance and back EMF term were considered. Then, the faulted model was transformed into the two synchronous dq-models: one for the positive sequence and the other for the negative sequence. Also, a torque equation, which shows the relation between the ripple and the negative sequence current, is derived. The negative sequence current should be suppressed to eliminate the torque ripple. The dual current controller is utilized for this purpose: in the dual controller, the positive and negative sequences are controlled separately in their own synchronous frames. Notch filters are utilized in each synchronous frame to extract positive or negative sequence component. Experiments were performed with an SPMSM specially designed to make an internal turn short artificially. The experimental results coincide well with the corresponding simulation results, and exhibit a strength of the dual current controller in suppressing the negative sequence current.

The development of a modified spectral ripple test

Abstract: Poor spectral resolution can be a limiting factor for hearing impaired listeners, particularly for complex listening tasks such as speech understanding in noise. Spectral ripple tests are commonly used to measure spectral resolution, but these tests contain a number of potential confounds that can make interpretation of the results difficult. To measure spectral resolution while avoiding those confounds, a modified spectral ripple test with dynamically changing ripples was created, referred to as the spectral-temporally modulated ripple test (SMRT). This paper describes the SMRT and provides evidence that it is sensitive to changes in spectral resolution.

High-Efficiency Asymmetrical Half-Bridge Converter Without Electrolytic Capacitor for Low-Output-Voltage AC–DC LED Drivers

Abstract: Due to their high reliability and luminous efficacy, high-brightness light-emitting diodes are being widely used in lighting applications, and therefore, their power supplies are required to have also high reliability and efficiency. A very common approach for achieving this in ac-dc applications is using a two-stage topology. The power factor corrector boost converter operating in the boundary conduction mode is a very common converter used as first stage. It is normally designed without electrolytic capacitors, improving reliability but also increasing the low-frequency ripple of the output voltage. The asymmetrical half-bridge (AHB) is a perfect option for the second stage as it has very high efficiency, it operates at constant switching frequency, and its output filter is small (i.e., it can be also easily implemented without electrolytic capacitors). Moreover, the AHB is an excellent candidate for self-driven synchronous rectification (SD-SR) as its transformer does not have dead times. However, the standard configuration of the SD-SR must be modified in this case in order to deal with the transformer voltage variations due to the input voltage ripple and, more important, due to the LED dimming state. This modification is presented in this paper. Another important issue regarding the AHB is that its closed-loop controller cannot be very fast and it cannot easily cancel the previously mentioned low-frequency ripple. In this paper, a feed-forward technique, specifically designed to overcome this problem, is also presented. The experimental results obtained with a 60-W topology show that efficiency of the AHB may be very high (94.5%), while the inherent control problems related to the AHB can be overcome by the proposed feed-forward technique.

An Active Damping Technique for Small DC-Link Capacitor Based Drive System

Abstract: A small dc-link capacitor based drive system shows instability when it is operated with large input line inductance at operating points with high power. This paper presents a simple, new active damping technique that can stabilize effectively the drive system at unstable operating points, offering greatly reduced input line current total harmonic distortion. The proposed method requires only a first-order, high-pass filter with a gain. Active damping voltage terms, linked directly to the dc-link voltage ripple through gain units, are injected to the drive machine for stabilizing the operating points. The stabilizing effect of the active damping terms is demonstrated for an induction machine based drive system. The effects of the added damping terms on the machine current and dc-link voltage are analyzed in detail. A design recommendation for the proposed active damping terms is given. Experimental results verifying the effectiveness of the new active damping method are presented.

A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement

Abstract: A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 mm2 in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 V/μs as well as the improved MIPS performance by 5.6 times was achieved.

Theoretical and Experimental Analysis for Current in a Dual-Inverter-Fed Open-End Winding Induction Motor Drive With Reduced Switching PWM

Abstract: A dual two-level voltage source inverter (VSI) can synthesize a three-level voltage space vector employing an open-end winding induction motor. Space-vector-based pulsewidth modulation (PWM) variants for this dual VSI are proposed in this paper that offer the dual advantage of limiting the switching power loss to a single VSI at all instants and also reducing the switching commutations in the dual VSI by 50%. The influence of different error volt seconds (affected with different PWM variants) on the motor phase current in the dual VSI is critically analyzed. To this end, two analytical approaches (one using error-voltage trajectory information and the other using switching state information of the dual VSI) are also proposed in this paper to predict the current trajectory and the ripple content in the drive system. Expressions for rms ripple current are developed with different PWM variants. The efficacy of the proposed analytical approaches to predict the current trajectory and the ripple content is confirmed from the experimental results. All the PWM variants are first simulated using MATLAB and verified experimentally by conducting tests on a three-phase open-end winding induction motor drive controlled with volts per hertz control. The implementation of the PWM algorithms only requires instantaneous magnitudes of three-phase reference voltages and completely avoids the sector identification and lookup tables.

Modeling and Analysis of Switching-Ripple Voltage on the DC Link Between a Diode Rectifier and a Modular Multilevel Cascade Inverter (MMCI)

Abstract: This paper focuses on the common dc-link voltage between a three-phase diode rectifier and a modular multilevel cascade inverter based on double-star chopper cells (MMCI-DSCC) for a medium-voltage motor drive. This motor drive can be operated even when no capacitor exists on the dc link. However, a nonnegligible, but predictable, amount of switching-ripple voltage occurs on the dc link. This paper achieves modeling and analysis of the switching-ripple voltage, thus making it possible to design a small-sized dc passive filter consisting of series connection of a film capacitor and a damping resistor. A 400-V, 15-kW down scaled system is used to confirm the effectiveness of the analysis and the dc filter. Experimental results show that the switching-ripple voltage can be attenuated satisfactorily by the dc filter, and that the power loss dissipated in the damping resistor is negligible, compared to the rated power of 15 kW.

Design and Control of a Grid-Connected Interleaved Inverter

Abstract: This paper is concerned with the design and control of a three-phase voltage source grid-connected interleaved inverter. This topology enables the use of low-current devices capable of switching at high frequency, which together with the ripple cancelation feature reduces the size of the output filter and the inverter considerably compared to an equivalent classical two-level voltage source inverter with an LCL output filter using high-current devices with considerably lower switching frequency. Due to its higher switching frequency and low-filter component values, the interleaved inverter also has a much higher bandwidth than the classical inverter, which improves grid voltage harmonics disturbance rejection and increases the speed of response of the inverter and its capability to ride through grid disturbance (e.g., voltage sags and swells). The paper discusses the selection of the number of channels and the filter component values of the interleaved inverter. The design of the digital control system is then discussed in detail. Simulation and practical results are presented to validate the design and demonstrate its capabilities.

Interleaved Boundary Conduction Mode (BCM) Buck Power Factor Correction (PFC) Converter

Abstract: An interleaved boundary conduction mode power-factor-correction buck converter that maintains high efficiency across entire load and line range is proposed. The adaptive master-slave interleaving method maintains stable 180° out-of-phase operation during any transient. By interleaving two parallel-connected buck converters, the input current ripple is halved while the ripple frequency is doubled, which leads to a smaller differential mode line filter. The line current harmonic distortion is analyzed to examine the allowable output voltage range while meeting harmonic regulations. The operation and performance of the proposed circuit is verified on a 300 W, universal line experimental prototype with 80 V output. The measured efficiencies remain above 96% down to 20% of full load across the entire universal line range. Even at 10% of full-load condition, the efficiency remains above 94%. The input current harmonics also meet the IEC61000-3-2 (class D) standard.

Energy harvesting from hydraulic pressure fluctuations

Abstract: State-of-the-art hydraulic hose and piping systems employ integral sensor nodes for structural health monitoring to avoid catastrophic failures. Energy harvesting in hydraulic systems could enable self-powered wireless sensor nodes for applications such as energy-autonomous structural health monitoring and prognosis. Hydraulic systems inherently have a high energy intensity associated with the mean pressure and flow. Accompanying the mean pressure is the dynamic pressure ripple, which is caused by the action of pumps and actuators. Pressure ripple is a deterministic source with a periodic time-domain behavior conducive to energy harvesting. An energy harvester prototype was designed for generating low-power electricity from pressure ripples. The prototype employed an axially-poled off-the-shelf piezoelectric stack. A housing isolated the stack from the hydraulic fluid while maintaining a mechanical coupling allowing for dynamic-pressure-induced deflection of the stack. The prototype exhibited an off-resonance energy harvesting problem since the fundamental resonance of the piezoelectric stack was much higher than the frequency content of the pressure ripple. The prototype was designed to provide a suitable power output for powering sensors with a maximum output of 1.2 mW. This work also presents electromechanical model simulations and experimental characterization of the piezoelectric power output from the pressure ripple in terms of the force transmitted into the harvester. (Some figures may appear in colour only in the online journal)

Ripple-Port Module-Integrated Inverter for Grid-Connected PV Applications

Abstract: The single-phase inverter has inherent double-frequency power ripple, which if not internally mitigated, appears at the input port and deteriorates the maximum power point tracker performance. Conventional dc link inverter topologies filter this significant double-frequency ripple by means of the bus capacitance, usually in the form of electrolytic capacitors, which have well known lifetime challenges. This paper presents a double-frequency ripple cancellation concept and experimental proof of concept. The proposed module-integrated inverter is based on the commonly used two-stage inverter. However, a third port is added for ripple cancellation purposes. Hence, a very small capacitance is needed, and, as a result, a high-reliability film capacitor can be used instead of the bulky low-reliability electrolytic ones.

Evaluation of current ripple amplitude in three-phase PWM voltage source inverters

Abstract: Determination of current ripple in three-phase PWM voltage source inverters (VSI) is important for both design and control purposes, since this is the most popular conversion topology for energy conversion systems. In this paper the complete analysis of the peak-to-peak current ripple distribution over a fundamental period is given for three-phase VSIs. In particular, peak-to-peak current ripple amplitude is analytically determined as a function of the modulation index. Minimum, maximum, and average values are also emphasized. Although the reference is made to continuous symmetric PWM, being the most simple and effective solution to minimize the current ripple, the analysis could be easily extended to either discontinuous or unsymmetrical modulation, both carrier-based and space vector PWM. The analytical developments for all the different subcases are verified by numerical simulations.

AC/DC Matrix Converter With an Optimized Modulation Strategy for V2G Applications

Abstract: To adapt the battery voltage and increase charging efficiency in vehicle to grid (V2G) systems, an ac/dc matrix converter topology is presented. Aim to solve the problem of relatively large charging current ripple in the classical current space vector modulation strategy, a sectional optimized modulation strategy, is proposed, which can reduce the charging current ripple within the whole output range. And the comparative analysis is carried out between them. A simple controller with active damping is briefly introduced; it can work at two charging modes: constant voltage charging and constant current charging. The simulation and experimental results demonstrate the validity and effectiveness of the proposed method.

Novel Interleaved Bidirectional Snubberless Soft-Switching Current-Fed Full-Bridge Voltage Doubler for Fuel-Cell Vehicles

Abstract: This paper presents a novel interleaved soft-switching bidirectional snubberless current-fed full-bridge voltage doubler (dc/dc converter) for an energy storage system in fuel cell electric vehicles. A novel secondary modulation technique is also proposed to clamp the voltage across the primary-side switches naturally with zero-current commutation. It, therefore, eliminates the necessity for an external active-clamped circuit or passive snubbers to absorb the switch turn-off voltage spike, a major challenge in current-fed converters. Zero-current switching of primary-side devices and zero-voltage switching of secondary-side devices are achieved, which significantly reduce switching losses. An interleaved design is adopted over a single cell to increase the power handling capacity obtaining merits of lower input current ripple, reduction of passive components' size, reduced device voltage and current ratings, reduced conduction losses due to current sharing, and better thermal distribution. Primary device voltage is clamped at rather low-reflected output voltage, which enables the use of low-voltage semiconductor devices having low on-state resistance. Considering input current is shared between interleaved cells, conduction loss of the primary side, a considerable part of total loss, is significantly reduced and higher efficiency can be achieved to obtain a compact and higher power density system. Steady-state operation, analysis, and design of the proposed topology have been presented. Simulation is conducted over software package PSIM 9.0.4 to verify the accuracy of the proposed analysis and design. A 500-W prototype has been built and tested in the laboratory to validate the converter performance.

Novel Random-Switching PWM Technique With Constant Sampling Frequency and Constant Inductor Average Current for Digitally Controlled Converter

Abstract: A new 2-D random-switching pulsewidth modulation (PWM) technique is proposed to reduce the dominant harmonic clusters while retaining constant average inductor current and constant sampling frequency. The special feature of constant average inductor current can reduce the output voltage ripple. Moreover, the controller parameters of a digitally controlled power converter are not required to change, which is quite essential to digitally controlled systems. Current random PWM methods are discussed and compared with the proposed method in this paper. It will be shown that the merits of the presented method include random-switching frequency, constant sampling frequency, and constant average inductor current. An field-programmable-gate-array-based digitally controlled buck converter experimental system has been set up. The specifications of the converter include input voltage = 5 V, output voltage = 1.5 V, and switching frequency = 200 kHz. The proposed random-switching pattern is implemented by software. Experimental results demonstrate the effectiveness of the proposed random-switching pattern.