Showing papers on "Schottky barrier published in 1980"

The Concept of Fermi Level Pinning at Semiconductor/Liquid Junctions. Consequences for Energy Conversion Efficiency and Selection of Useful Solution Redox Couples in Solar Devices

Abstract: Fermi level pinning refers to a situation where the band bending in a semiconductor contacting a metal is essentially independent of the metal even for large variation in the work function of the metal. It was found that a similar situation sometimes results for a semiconductor contacting liquid electrolyte solutions containing redox couples having very different electrochemical potentials. Recently, workers in the field of semiconductor photoelectrochemistry have emphasized a limiting case of the model of the semiconductor/liquid interface where the drop across the semiconductor depends on applied potential; at equilibrium with the solution, the band bending is generally regarded as varying with changes in the solution potential by virtue of changes in the redox couple or simply changing the ratio of oxidized and reduced material. Fermi level pinning results in semiconductor/liquid interfaces which can be viewed as analogous to a Schottky barrier photocell in series with an electrochemical cell in that the extent to which a given redox process can be driven uphill is independent of the potential of the redox couple.n-GaAs, p-GaAs, p-GaAs, and p-Si are semiconductors that exhibit Fermi level pinning in liquid electrolyte solutions (CH/sub 3/CN/(n-Bu/sub 4/N)ClO/sub 4/) of redox reagents. Fermi level pinning has the disadvantagemore » in practical terms of limiting photovoltage in optical energy conversion applications, but such a phenomenon allows the use of a very wide range of solution couples. Since Fermi level pinning results from surface states, changes in the surface brought about by deliberate surface chemistry may change the surface states and hence the photovoltage in solid-state and liquid-junction solar devices.« less

Measurement of isotype heterojunction barriers by C‐V profiling

Abstract: The Debye length smearing that occurs in C‐V profiling has precluded the use of C‐V profiling from an adjacent Schottky barrier to measure the magnitude of energy band discontinuities at barriers in isotype heterojunctions. It is observed, however, that in such a process both the number of the charge carriers and the moment of their distribution are conserved. This information permits the extraction of values for both the conduction band discontinuity ΔEc and any interface charge density. This technique and experimental results for an LPE‐grown n‐N GaAs‐Al0.3Ga0.7As heterojunction are described. We find ΔEc =0.248 eV, corresponding to about to 0.66ΔEg rather than Dingle’s commonly accepted value 0.85ΔEg . The difference is attributed to compositional grading during LPE growth.

Degradation mechanism of non-Ohmic zinc oxide ceramics

Abstract: The degradation phenomena caused by dc and ac biasing in non‐Ohmic ZnO ceramics are studied from the viewpoints of voltage (V)‐current (I) characteristics, dielectric properties, and thermally stimulated current (TSC). As a result, it is concluded that the degradation caused by dc biasing is attributed to the asymmetrical deformation of Schottky barriers, due to ion migrations in Bi2O3‐rich intergranular layers and in the depletion layers of the Schottky barriers; and that the degradation caused by ac biasing is attributed to the symmetrical deformation of the Schottky barriers, due to ion migration in the depletion layers of the Schottky barriers. Also, the relationship between the thermal runaway life of non‐Ohmic ZnO ceramics and biasing conditions, such as biasing temperature and bias voltage, is obtained.

Fabrication and numerical simulation of the permeable base transistor

Abstract: A new transistor structure has been reported in which a thin tungsten grating has been embedded inside a single crystal of gallium arsenide. The embedded metal grating, which forms a Schottky barrier with the gallium arsenide, is the base of the transistor and can be used to raise and lower a potential barrier in the semiconductor between the grating lines. The name given to this device is the permeable base transistor (PBT). Devices have been fabricated with a noise figure of 3.5 dB, an associated gain of 9 dB at 4 GHz, and a maximum frequency of oscillation of 17 GHz. This transistor structure is numerically modeled over a wide range of metal grating thicknesses, periodicities, and carrier concentrations. The results from these simulations have been condensed into a unified equation for the base-to-collector transfer characteristic which is valid for the PBT, FET's, and bipolar transistors, and simplifies the comparison between different device structures. A new iterative technique has been used to approximate the nonequilibrium electron velocity, leading to a predicted f T above 200 GHz, a maximum frequency of oscillation near 1000 GHz and a power-delay product below 1 fJ for devices with small grating dimensions and large carder concentrations.

Parallel silicide contacts

Abstract: Parallel silicide contacts consisting of PtSi and NiSi with fixed ratios of contact areas were prepared for current‐voltage and capacitance‐voltage measurements of Schottky barrier height. These measurements were analyzed with models assuming a linear combination of thermionic emission currents or junction capacitances. The measured and the computed values of barrier height have been found to agree very well. A systematic diagnosis of parallel contacts under a variety of conditions is presented in the Appendix.

Feasibility of hybrid Josephson field effect transistors

Abstract: We consider the feasibility of fabricating planar superconductor‐semiconductor‐superconductor Josephson junctions in which the junction supercurrent is controlled by a gate electrode isolated from the junction by either a dielectric film (MOS‐JOFET) or a Schottky barrier (MES‐JOFET). We find that device critical currents between ∼1 and 100 μA and critical temperatures approximately a few K appear possible. We discuss the circuit applications of such devices.

Interpretation of the conductance and capacitance frequency dependence of hydrogenated amorphous silicon Schottky barrier diodes

Abstract: We present a general model of the frequency dependence of conductance and capacitance in a‐Si:H Schottky diodes. In order to circumvent several questionable assumptions required in the analysis of capacitance voltage characteristics, the frequency dependence of sputtered a‐Si:H devices is measured with no applied dc voltage. We obtain independent, consistent values of the depletion width and of the density of states at the Fermi level and below from both conductance and capacitance at both low and high modulation frequencies. We show that the linear frequency dependence of conductance cannot be attributed to hopping conductance, but rather to the interaction of gap states with free carriers. Our study shows that the interaction kinetics of the states around the Fermi level with the conduction‐band carriers is so fast that the response of the diode is limited by the band transport of these carriers, which rapidly thermalize and distribute themselves through the continuum of states from the conduction band ...

Method of fabricating MOS field effect transistors

Abstract: A method for making a MOSFET device (20) in a semiconductor body (10) includes the step of forming source and drain contact electrodes (12.1, 12.2) prior to growth of the gate oxide (10.3) and after formation of a high conductivity surface region (10.5). The exposed mutually opposing sidewall edges of each of the contact electrodes (12.1, 12.2) are coated with a sidewall silicon dioxide layer (15.1, 15.2), and the then exposed surface of the semiconductor body (10) between these sidewalls is etched to depth beneath the high conductivity surface region (10.5) in order to separate it into the source and drain regions (10.1, 10.2). Formation of the high conductivity region may be omitted by using Schottky barrier or impurity doped material for the contact electrodes (12.1, 12.2).

Applications of Electrochemical Methods for Semiconductor Characterization I . Highly Reproducible Carrier Concentration Profiling of VPE “Hi‐Lo”

Abstract: Factors which influence the accuracy and reproducibility of semiconductor carrier concentration profiling via capacitance‐voltage measurements and dissolution at an electrolytic Schottky barrier are critically examined. Attention is centered upon the capacitance contributions from the edge regions of the electrolyte contact area. It is shown that several properties of the electrolyte, and the measurement frequency, as well as the physical means of electrolyte confinement have an important influence. In particular, a suitable combination of electrolyte conductivity, wetting, and dissolution behavior can be met by 0.1M Tiron, for the profiling of using the "Post Office Profile Plotter." Examples are given which demonstrate the high degree of reproducibility, both short‐ and long‐term, attainable for the profiling of "hi‐lo" structures. Optimization of the approach for other semiconductor materials, for which an "ideal" electrolyte may not be available, is also discussed.

Influence of the image force on the band gap in semiconductors and insulators

Abstract: The change in potential energy of electrons and holes and the resulting band‐gap change caused by the image force have been calculated close to the insulator‐semiconductor interface. Some examples are given from which it appears that in metal‐insulator‐semiconductor (MIS) structures, as in Schottky diodes, the effects of the image force should not be overlooked.

Electrical Defects in Silicon Introduced by Sputtering and Sputter‐Etching

Abstract: Sputtering a gold contact on n‐silicon or sputter‐etching the silicon surface prior to deposition of gold results in a Schottky barrier which shows a barrier height which depends on the sputtering voltage and time, and is lower than a corresponding barrier obtained by evaporation of a gold contact. On p‐silicon a sputtered gold contact also shows a barrier height influenced by the sputtering conditions. The modifications of the barrier height are caused by a thin positively charged layer formed in the semiconductor near the metal‐semiconductor junction. During sputter etching the silicon surface is subject to bombardment by Ar ions with energies of about the sputtering voltage. If this voltage is high enough charged centers will be introduced. These centers are also observed after sputter deposition at high voltage. We found that damage is caused by etching at 500V but not at 100V. This indicates that the damage found after sputter deposition was caused by rebounded Ar atoms.

Interfacial layer theory of the Schottky barrier diodes

Abstract: The interfacial layer theory considering the surface fixed charge and the voltage drop across the interfacial layer is developed for the Schottky barrier diodes fabricated on the n‐type semiconductor substrate. It is shown that the positive surface fixed charge will reduce the barrier height and then increases the reverse current; the voltage drop across the interfacial layer will increase the ideality factor of the forward biased I‐V characteristic and the voltage dependence of the reverse‐biased I‐V characteristic, aside from the effects of the image force lowering; the fluctuations of the experimental data deduced from the fabricated Schottky barrier diodes with different fabricating conditions are mainly due to the variations of the interfacial‐layer properties such as the interfacial‐layer thickness, the interface states, the surface fixed charges.

Capacitance studies on amorphous silicon Schottky barrier diodes

Abstract: The capacitance C of Schottky barrier diodes prepared by the deposition of Pt onto undoped and phosphorus doped a-Si:H films is studied as a function of frequency f, temperature T and applied voltage V. With increasing f and decreasing T the capacitance decreases by factors as large as 10 indicating that the space charge is located in deep gap states with response times which in part are greater than 103s. The behaviour of Schottky barriers in undoped a-Si:H can well be described in terms of a model with an energy independent density of states close to 1017cm−3eV−1. Doping with PH3 results in an increase of C, accompanied by a decrease in barrier width and barrier height. Fot T > 300 K and V > 0.3 V a strong increase of C is observed which is tentatively attributed to the contribution of interface states.

Evidence of space-charge-limited current in amorphous silicon Schottky diodes

Abstract: Palladium/amorphous silicon (a-SiH x ) Schottky barrier diodes have been found to exhibit superlinear dark forward current-voltage (I-V) characteristics over the temperature range 30 to 130°C. The results are consistent with expected behavior for space-charge-limited current in the presence of distributed traps. The trap parameters are deduced from I-V data.

Orientation effect on planar GaAs Schottky barrier field effect transistors

Abstract: Orientation effects on planar GaAs Schottky barrier field effect transistors (MESFET’s) have been found Device characteristics of FET’s parallel to both [110] directions and both [100] directions are compared Dependence of the characteristics on gate length has been measured for FET’s oriented in two perpendicular [110] directions Preferential lateral diffusion is proposed to be the reason underlying these phenomena

Surface vacancies in InP and GaAlAs

Abstract: We present calculations of the bound‐state energy levels of ideal vacancies near the (110) surface of InP and GaAlAs. We find that there is a strong correlation between the the calculated position of the highest filled anion vacancy level in the neutral vacancy and the measured Fermi level at the surface. This correlation suggests that the recently proposed defect model of Schottky barrier formation is capable of accounting for the observed trends in Schottky barrier formation and that the states responsible in III‐V semiconductors are related to defects which introduce dangling cation bonds.

Determination of the electronic density of states in hydrogenated amorphous silicon (a-SiH) from Schottky diode capacitance-voltage and conductance-voltage measurements

Abstract: We describe the method of determination of N(E) by means of Schottky diode capacitance-voltage C(V) and conductance-voltage G(V) measurements versus frequency. We characterize sputtered a-SiH (optical gap = 1.9 V, [H] = 15 % at.) using Pt and Au Schottky diodes. The main features of N(E) are the following (in the upper part of the gap) : 1. 1/ the density of states around the midgap E i is about 10 16 cm −3 eV −1 ; 2. 2/ a peak in the density of states seems to emerge at 0.4 eV above E i , which is attributed to weak SiSi bonds ; 3. 3/ a surprisingly large conduction “band-tail” of 0.45 eV is measured above can be interpreted as being due to SiH anti-bounding states which could be observed in such a wide gap material.

Surface point defects and Schottky barrier formation on ZnO(101̄0)

Abstract: We have created well‐defined concentrations of surface point defects (oxygen vacancies, Vos) on ZnO(1010) surfaces under controlled UHV conditions and have tested their influence on Schottky barrier formation. ZnO(1010) with and without surface defects exhibit almost identical Schottky barrier features, independent of the evaporated metal. Surface work function and band bending variations with metal coverage are qualitatively different for Au vs Al interfaces, regardless of defect concentration. Barrier formation occurs relatively slowly for Au on ZnO, while Al on ZnO induces a pronounced dipole with the first half monolayer.

Rare earth silicide Schottky barriers

Abstract: In the practice of this disclosure, rare earth disilicide low Schottky barriers (≲0.4 eV) are used as low resistance contacts to n-Si. Further, high resistance contacts to p-Si (Schottky barrier of ≳0.7 eV) are also available by practice of this disclosure. A method is disclosed for forming contemporaneously high (≳0.8 eV) and low (≲0.4 eV) energy Schottky barriers on an n-doped silicon substrate. Illustratively, the high energy Schottky barrier is formed by reacting platinum or iridium with silicon; the low energy Schottky barrier is formed by reacting a rare earth with silicon to form a disilicide. Illustratively, a double layer of Pt/on W is an effective diffusion barrier on Gd and prevents the Gd from oxidation.

Pd/Ge contacts to n-type GaAs

Abstract: Sintered metal-semiconductor contacts, formed by thin, evaporated layers of Pd and Ge on n -type GaAs, were studied using Auger electron spectroscopy, X-ray diffraction, X-ray photoelectron spectroscopy, secondary ion mass spectroscopy, current-voltage measurements, and capacitance-voltage measurements. Prior to sintering, the as-deposited Pd/Ge/GaAs contacts were rectifying and exhibited a reproducible Schottky barrier energy φ Bn of 0.67±0.02 eV. Auger analysis indicated the initial behavior of the contact structure, upon sintering, to be an interdiffusion and reaction of Pd and Ge on a non-reacting GaAs substrate. Two germanide phases, Pd 2 Ge and PdGe, were identified using X-ray diffraction and Auger analysis. The intervening Ge layer prevented the reaction of Pd with the GaAs substrate at low temperatures. Because of the PdGe reaction, φ Bn increased to approximately 0.85 eV. Sintering at higher temperatures (i.e. between 300 and 400°C) produced additional reactions between Pd and the GaAs substrate. The electrical properties of the contact remained rectifying and φ Bn exhibited little change from the value of 0.85 eV with the interdiffusion of Pd, Ga, and As. Sintering above 400°C resulted in the formation of ohmic contacts. The diffusion of Ge to the GaAs interface was found to correlate with the onset of ohmic behavior. Current conduction in the contact was best described by thermionic-field emission theory, and a specific contact resistance of 3.5 × 10 −4 Ω-cm 2 was obtained after sintering above 550°C, independent of the initial impurity concentration in the substrate. Over the entire range of sintering temperatures (i.e. at or below 600°C), the interaction between the thin-film layers appeared to be governed by diffusion-controlled, solid-phase processes with no evidence of the formation of a liquid phase. As a result, the surface of the contact structure remained smooth and uniform during sintering.

Energy levels of semiconductor surface vacancies

Abstract: We present calculations of the bound state energy levels of anion vacancies near the surface of a III–V semiconductor. We consider the (110) surface of GaAs, InP, and the Ga_(1−x)Al_(x)As alloy system. As the vacancy is moved toward the surface, the energy levels are only slightly perturbed until the vacancy reaches the second atomic layer from the surface. At this point, the anion vacancy levels move to lower energy. We find that there is a general trend in the vacancy energy levels with semiconductor ionicity. As the material becomes more ionic, the anion vacancy levels move to higher energy. Comparing this trend with experimentally observed Schottky barrier heights, we find a strong correlation between the position of the highest occupied level in the anion vacancy and the measured Fermi level at the surface. This result suggests that the recently proposed defect model is capable of accounting for observed trends in Schottky barrier formation.