Showing papers on "Silicon on insulator published in 1993"

Silicon-based optoelectronics

Abstract: The decade of the 1990's is an opportune time for scientists and engineers to create cost-effective silicon "superchips" that merge silicon photonics with advanced silicon electronics on a silicon substrate. We can expect significant electrooptical devices from Column IV materials (Si, Ge, C and Sn) for a host of applications. The best devices will use strained-layer epitaxy, doped heterostructures, and bandgap engineering of quantum-confined structures. This paper reviews Si-based photonic components and optoelectronic integration techniques, both hybrid and monolithic. >

Scaling theory for double-gate SOI MOSFET's

Abstract: A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate

Abstract: A method of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI wafer includes a silicon layer separated from a bulk silicon substrate by a layer of dielectric material, typically SiO2. Next, at least one electrical feedthrough is formed in each of the silicon layers and active and passive devices are formed in each of the thin silicon layers. Next, interconnects are formed that overlie the silicon layer and are electrically coupled to the feedthrough. One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then etched to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit.

Method of producing a thin silicon-on-insulator layer

Abstract: A method of forming a thin silicon SOI layer by wafer bonding, the thin silicon SOI layer being substantially free of defects upon which semiconductor structures can be subsequently formed, is disclosed. The method comprises the steps of: a) providing a first wafer comprising a silicon substrate (10) of a first conductivity type, a diffusion layer (12) of a second conductivity type formed thereon and having a first etch characteristic, a thin epitaxial layer (14) of the second conductivity type formed upon the diffusion layer and having a second etch characteristic different from the first etch characteristic of the diffusion layer, and a thin oxide layer (16) formed upon the thin epitaxial layer; b) providing a second wafer comprising a silicon substrate (18) having a thin oxide layer (20) formed on a surface thereof; c) wafer bonding said first wafer to said second wafer so that said thin oxide layers (16,20) bond to form a thick oxide layer (22); d) removing the silicon substrate (10) of said first wafer in a controlled mechanical manner; and e) removing the diffusion layer (12) of said first wafer using a selective dry low energy plasma process to expose the underlying thin epitaxial layer (14), the selective dry low energy plasma process providing an etch ratio of the first etch characteristic to the second etch characteristic such that the diffusion layer is removed with minimal formation of any shallow plasma radiation damage to the exposed underlying thin epitaxial layer. The exposed thin epitaxial layer (14) may be then used as standard to form active/passive devices.

Silicon carbide switching device with rectifying-gate

Abstract: A silicon carbide switching device includes a three-terminal interconnected silicon MOSFET and silicon carbide MESFET (or JFET) in a composite substrate of silicon and silicon carbide. For three terminal operation, the gate electrode of the silicon carbide MESFET is electrically shorted to the source region of the silicon MOSFET, and the source region of the silicon carbide MESFET is electrically connected to the drain of the silicon MOSFET in the composite substrate. Accordingly, three-terminal control is provided by the source and gate electrode of the silicon MOSFET and the drain of the silicon carbide MESFET (or JFET). The switching device is designed to be normally-off and therefore blocks positive drain biases when the MOSFET gate electrode is shorted to the source electrode. At low drain biases, blocking is provided by the MOSFET, which has a nonconductive silicon active region. Higher drain biases are supported by the formation of a depletion region in the silicon carbide MESFET (or JFET). To turn-on the device, the gate electrode is biased positive and an inversion layer channel of relatively low resistance is formed in the silicon active region. The channel electrically connects the source of the silicon carbide MESFET (or JFET) with the source of the silicon MOSFET to thereby turn-on the device when a positive drain bias is applied.

Substrate for tensilely strained semiconductor

Abstract: A structure with strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.

Semiconductor thin film formed on a supporting substrate

Abstract: A semiconductor substrate is provided which has a semiconductor on insulator structure but in which can be formed a thin film integrated circuit having electrical characteristics and microstructure equal to or of greater density than a silicon integrated circuit formed using a bulk single crystal silicon wafer. The semiconductor substrate has a structure which is formed of a sequentially layered single crystal silicon thin film sandwiched between a thermally oxidized silicon film and a silicon oxide or silicon nitride film, an element smoothing layer, a fluoro-epoxy series resin adhesive layer, and a supporting substrate. The single crystal silicon thin film can have integrated circuit devices formed in a sub-micron geometry similar to that of a bulk single crystal silicon. A transparent glass or a bulk single crystal silicon wafer can be used as a supporting substrate. Therefore the semiconductor thin film can integrate a highly fine, dense and compact semiconductor integrated circuit or semiconductor optical element. The semiconductor thin film element has a transparent optical detection region or optical modulation region with 100 million pixels or more.

Method for forming silicon on a glass substrate

Abstract: A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics.

Silicon-on-insulator capacitive surface micromachined absolute pressure sensor

Abstract: A method and structure for forming a capacitive transducer having a deformable single crystal diaphragm. A first well region is formed within a semiconductor substrate in an SOI wafer having a sacrificial layer of known thickness and a top single-crystal silicon layer thereon. Next, a silicon epitaxial layer is deposited on the top silicon layer for forming a flexible single crystal membrane. The epitaxial layer and the sacrificial layer are masked and etched to define the flexible diaphragm. An electrical insulating conformal support layer is deposited on the substrate and attached to the diaphragm so as to seal the sacrificial layer therebetween. An access opening is etched through the diaphragm, and then a wet etchant is inserted through the access opening for removing the sacrificial layer, thereby defining a diaphragm cavity between the remaining epitaxial layer and the substrate. The thickness of the diaphragm cavity is substantially equal to the thickness of the sacrificial layer removed from the SOI wafer. Conductive ions are diffused into facing sections of the diaphragm and the first well of the substrate so as to define fixed and deformable electrodes of the sensing capacitor. Next, a plug is selectively deposited within and for sealing the access opening without substantially reducing the volume of the diaphragm cavity. In this manner, a deflection of the flexible diaphragm in response to variations between the ambient pressure and the pressure sealed within the diaphragm cavity causes a o corresponding change in the capacitance between the first well region and the conductive region in the diaphragm. A reference capacitive sensor of similar construction is also provided for ratiometric pressure measurements. A pressure transducer manufactured in accordance with this process is also described.

Process for the production of accelerometers using silicon on insulator technology

Abstract: A process for the production of accelerometers using the silicon on insulator method. The process comprises the following stages: a) producing a conductive monocrystalline silicon film on a silicon substrate and separated from the latter by an insulating layer; b) etching the silicon film and the insulating layer up to the substrate in order to fix the shape of the mobile elements and the measuring devices; c) producing electric contacts for the measuring devices; d) partial elimination of the insulating layer in order to free the mobile elements, the remainder of the insulating layer rendering integral the substrate and the moving elements.

Method of forming an ultra-uniform silicon-on-insulator layer

Abstract: A method of forming a thin semiconductor layer having ultra-high thickness uniformity and upon which semiconductor structures can subsequently be formed is disclosed. The method comprises providing a primary substrate having a prescribed total thickness variation (TTV). A stack is formed upon the primary substrate for compressing thickness variation to be transferred into the thin semiconductor layer. An epitaxial silicon layer of a desired SOI thickness is formed upon the stack. The epitaxial silicon layer is then bonded to a mechanical substrate to form a bonded substrate pair, the mechanical substrate having a prescribed TTV and the bonded substrate pair having a combined TTV equal to the sum of the TTVs of the primary and mechanical substrates, respectively. The primary substrate is subsequently removed, wherein the combined TTV of the bonded substrate pair is transferred and compressed into the stack by a first compression amount. The stack is thereafter removed, wherein the combined TTV of the bonded substrate pair is further transferred and compressed a second compression amount into said epitaxial silicon layer, whereby said epitaxial silicon layer remains on said mechanical substrate to form the semiconductor layer of ultra-high thickness uniformity, the thickness uniformity being a controlled function of the first and second compression amounts.

MICROX-an all-silicon technology for monolithic microwave integrated circuits

Abstract: An improved silicon-on-insulator (SOI) approach offers devices and circuits operating to 10 GHz by providing formerly unattainable capabilities in bulk silicon: reduced junction-to-substrate capacitances in FETs and bipolar transistors, inherent electrical isolation between devices, and low-loss microstrip lines. The concept, called MICROX (patent pending), is based on the SIMOX process, but uses very-high-resistivity (typically>10000 Omega -cm) silicon substrates, MICROX NMOS transistors of effective gate length 0.25 mu m give a maximum frequency of operation, f/sub max/, of 32 GHz and f/sub T/ of 23.6 GHz in large-periphery (4 mu m*50 mu m) devices with no correction for the parasitic effects of the pads. The measured minimum noise figure is 1.5 dB at 2 GHz with associated gain of 17.5 dB, an improvement over previously reported values for silicon FETs. >

Silicon MOSFETs, the microwave device technology for the 1990s

Abstract: Silicon MOSFET technology using 1.5- mu m gate lengths has demonstrated excellent performance for 900-MHz applications. Circuit results for low-noise amplifiers, power amplifiers, mixers, and oscillators using this technology are discussed in comparison to other device technologies. Device results for 0.6- mu m-gate-length devices showing the microwave performance of silicon MOS transistors are discussed. These results, together with scaling predictions, indicate that microwave silicon MOSFETs will play a major role in the 1990s. The performance of devices with 0.6- mu m gate lengths indicates that silicon MOS will be the FET technology of choice for applications below 3 GHz. Advantages such as high voltage characteristics, low thermal conductivity of silicon, and the high operating junction temperature make silicon MOS a technology with immense potential for high-voltage X-band power applications. >

Semiconductor memory cell with SOI MOSFET

Abstract: A dynamic semiconductor memory cell 72 includes a trench 81 having an insulating film 74 that is used as a dielectric material of a memory capacitor, and a MOSFET 80 that is formed by a process including a step of transforming a polysilicon film 85 on the insulating film 74 into a single crystal. The adjacent trenches are insulated by the insulating film 74 and the MOSFET of the Semiconductor-on-Insulator structure is used to provide a structure which can prevent a leak current, does not need highly accurate mask positioning, and can provide a higher degree of integration. The SOI MOSFET is deposited on the same insulating film 74 that is used as a dielectric material in the capacitor. By keeping the surface of the insulating film 74 over the substrate 71 flush with that of the storage electrode layer 73 the SOI MOSFET can be formed without a contact opening step for the source 76.

Soi actuators and microsensors

Abstract: The present invention relates to the fabrication of diaphragm pressure sensors utilizing silicon-on-insulator technology where recrystallized silicon forms a diaphragm which may incorporate electronic devices used in monitoring pressure. The diaphragm is alternatively comprised of a silicon nitride having the necessary mechanical properties with a recrystallized silicon layer positioned thereon to provide sensor electronics.

SOI MOSFET with floating gate

Abstract: A semiconductor device of an SOIMOSFET comprising a semiconductor substrate, an insulating layer and a thin film single-crystalline semiconductor layer, the insulating layer containing a floating electrically conductive layer buried therein at a portion corresponding to the channel, the floating electrically conductive layer being electrically insulated from the other portions, the semiconductor device further comprising an electrode adjacent to the floating electrically conductive layer for applying a voltage by which an electric charge is injected into and stored in the floating electroconductive layer.

Semiconductor memory device

Abstract: PURPOSE:To enable an SOI structure to be lessened in surface level difference, micronized, enhanced in density, and lessened in cell area. CONSTITUTION:A single-crystal silicon layer 4 formed by turning an amorphous silicon layer 3 into single crystal is laminated on the surface of a single-crystal silicon substrate 1 through intermediary of an insulating layer 2 to constitute an SOI structure, the source region 12 and the drain region 13 of an N-channel MOSFET 5 are formed by use of the single-crystal silicon layer 4, a capacitor 6 is formed in the insulating layer 2 vertically overlapping the N-channel MOSFET 5, the storage node 16 of the capacitor 6 is brought into contact with the side and the upside of the source region 12 of the N-channel MOSFET 5.

Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode

Abstract: A lateral Semiconductor-On-Insulator (SOI) device includes a substrate, a buried insulating layer on the substrate, and a lateral semiconductor device such as an LDMOS transistor, an LIGBT or a lateral thyristor on the insulating layer. The semiconductor device (in the case of an LDMOS transistor) includes a source region, a channel region, an insulated gate electrode over the channel region, a lateral drift region formed of a continuous layer of a lightly-doped semiconductor material on the buried insulating layer, and a drain contact region which is laterally spaced apart from the channel region and connected to the channel region by the drift region. A buried diode is formed in the substrate, and is electrically coupled to the drain contact region by a portion of the drift region which extends laterally in the region between the drain contact region and the buried diode.

Polysilicon pillar heat sinks for semiconductor on insulator circuits

Abstract: A heat sink is formed on a bonded semiconductor on insulator (SOI) wafer A trench is formed which extends from a top of the bonded SOI wafer through an isolation region of the bonded SOI wafer to a base of the bonded SOI wafer The base of the bonded SOI wafer is located below the isolation region of the bonded SOI wafer A conductive pillar is formed in the trench The conductive pillar extends from the top of the bonded SOI wafer through the isolation region of the bonded SOI wafer and is physically in contact with but electrically insulated from the base of the bonded SOI wafer In the preferred embodiment, the conductive pillar is formed of doped polysilicon The doped polysilicon is of a conductivity type which is different than the conductivity type of the base Out-diffusion from the doped polysilicon forms a region within the base which electrically insulates the conductive pillar from the base

High voltage structures with oxide isolated source and resurf drift region in bulk silicon

Abstract: An integrated circuit RESURF LDMOS power transistor combines SOI MOS technology with RESURF LDMOS technology to provide a source isolated high voltage power transistor with low "on" resistance for use in applications requiring electrical isolation between the source and substrate.

Demonstration of the potential of accumulation-mode MOS transistors on SOI substrates for high-temperature operation (150-300 degrees C)

Abstract: Measurements of accumulation-mode (AM) MOS SOI transistors in the 150-300 degrees C temperature range are reported and discussed. The increases of the threshold voltage shift and off leakage current with temperature of these SOI p-MOSFETs are observed to be much smaller than their bulk equivalents. Simple models are presented to support the experimental data. >

Method for forming SOI structure

Abstract: An epitaxially grown layer having a large area and an uniform thickness is formed on an insulating layer The surface of a silicon substrate (2) is oxidized to form a silicon dioxide layer (4) acting as insulating layer The silicon dioxide layer (4) is then provided with an opening (10) by etching with the aid of resist (6) After removing the resist (6), a silicon seed crystal layer (11) is selectively grown in the opening (10) Next, the silicon dioxide layer (4) is subjected to etchback using hydrofluoric acid, so that the side face (14) of the seed crystal layer (11) is emerged The following epitaxial growth on the basis of the seed crystal layer (11) is allowed sufficient growth in the lateral direction As a result, an epitaxially grown layer having (16) a large area and an uniform thickness is realized

Dual-gated semiconductor-on-insulator field effect transistor

Abstract: A method for forming a dual-gated Semiconductor-On-Insulator (SOI) field effect transistor for integrated circuits includes the formation of a gate/oxide/channel/oxide/gate stack on top of an insulating layer. The process begins with the formation of a first gate electrode and first oxide layer on an insulating layer. Then, a seed hole in the insulating layer is formed exposing the underlying substrate. This is followed by the epitaxial lateral overgrowth (ELO) of monocrystalline silicon, for example, from the seed hole to on top of the first oxide layer. This monocrystalline layer forms the device channel. A second oxide and second gate electrode layer are then grown and deposited, respectively. Subsequent etch steps employing sidewall spacers are then employed to form a multilayered stack having self-aligned first and second gate electrodes. Sidewall seed holes are then used to epitaxially grow monocrystalline source and drain regions from the channel. In-situ doping can be provided to form a lightly doped source (LDS) and drain (LDD) structure with vertically displaced source and drain contacts.

Process for producing a pressure transducer using silicon-on-insulator technology

Abstract: A process for producing a pressure transducer or sensor using the silicon-on-insulator method is provided. The process includes the following steps: (a) producing a monocrystalline silicon film (44) on a silicon substrate (6) at least locally separated from the latter by an insulating layer (42), (b) producing an opening (24) in the silicon film down to the insulating layer, (c) partially eliminating the insulating layer via the opening in order to form the diaphragm in the silicon film, and (d) resealing the opening (26).

Fabrication and Bonding Strength of Bonded Silicon-Quartz Wafers

Abstract: A multiply repeated process of thinning of silicon layer and annealing of the bonded silicon-quartz interface is proposed for tight bonding between a silicon wafer and a quartz wafer which have different thermal expansion coefficients. Silicon layers on quartz with a thickness of 2 µm±0.5 µm were debonded by a high temperature annealing over 650 C, whereas in the case of thinner silicon layers with a thickness under 0.5 µm tensile strengths over 80 MPa (800 kgf/cm2) were obtained in the temperature range from 700 C to 1100 C.

Semiconductor substrate having a silicon-on-insulator structure and method of fabricating the same

Abstract: The invention provides a silicon-on-insulator semiconductor substrate structure and a method of fabricating the same. The structure includes a base silicon substrate, a mono-crystalline silicon film formed on the base silicon substrate in a predetermined region, a poly-crystalline silicon film formed on the base silicon substrate in opposite region to the predetermined region, an insulator film formed on the polycrystalline silicon film, and a mono-crystalline silicon layer overlaying both the insulator film and the mono-crystalline silicon film so that the mono-crystalline silicon layer is electrically connected to the base silicon substrate through the mono-crystalline silicon film. The mono-crystalline silicon film permits not the mono-crystalline silicon layer only but also the base silicon substrate to serve as active regions.

Optimization of series resistance in sub-0.2 /spl mu/m SOI MOSFETs

Abstract: The optimization of device series resistance in ultra-thin film SOI devices is studied through 2-D simulations and process experiments. To achieve low series resistance, very thin silicides that do not fully consume the SOI film are needed. A novel cobalt salicidation technology using titanium/cobalt laminates is used to demonstrate sub-0.2 /spl mu/m, thin-film SOI devices with excellent performance and very low device series resistance. >

Low-power 1/2 frequency dividers using 0.1- mu m CMOS circuits built with ultrathin SIMOX substrates

Abstract: Four types of frequency dividers were fabricated on SIMOX/SOI (separation by implanted oxygen/silicon on insulator) substrates. A novel circuit among these four circuits showed the highest operation frequency of 1.2 GHz under 1-V supply voltage, with gate lengths of 0.15 and 0.1 mu m. Power consumption was no more than 50 and 62 mu W for both 0.15- and 0.1- mu m gate designs, respectively. >

Forming a device dielectric on a deposited semiconductor having sub-layers

Abstract: A high quality dielectric layer, typically silicon dioxide, is formed on a multi-layer deposited semiconductor structure, typically polysilicon or amorphous silicon. The multi-layer structure is formed by varying the silicon deposition rate so as to obtain a low stress deposited silicon structure. The low stress allows for a higher quality dielectric to be formed on the exposed top surface. One application is for thin film transistor gate oxides. Other applications included capacitor dielectrics and the tunnel oxide on the floating gate of EEPROMs.

SOI LIGBT devices with a dual P-well implant for improved latching characteristics

Abstract: The authors explore the inherent tradeoff between latching current density and threshold voltage in a typical lateral insulated-gate bipolar transistor (LIGBT), which uses a shallow implant and long drive-in to form its P-well. The latching performance of LIGBTs in silicon-on-insulator (SOI) substrates is compared to that of equivalent devices in bulk silicon. Two techniques are proposed for improving the latchup/threshold tradeoff in these SOI devices. Retrograde P-well implants are shown to yield significant improvements while adding little complexity to the fabrication process. Dual P-well implants are shown to effectively decouple the latching current from the threshold voltage, yielding LIGBTs with latching current densities over 1300 A/cm/sup 2/. >