Showing papers on "Spice published in 1992"
TL;DR: In this article, a physically based large signal heterojunction bipolar transistor (HBT) model is presented to account for the time dependence of the base, collector, and emitter charging currents, as well as self heating effects.
Abstract: A physically based, large signal heterojunction bipolar transistor (HBT) model is presented to account for the time dependence of the base, collector, and emitter charging currents, as well as self heating effects. The model tracks device performance over eight decades of current. The model can be used as the basis of SPICE modeling approximations, and to this end, examples are presented. A thesis for the divergence of high frequency large signal SPICE simulations from measured data is formulated, including a requisite empirical equation for the base-collector junction capacitance. >
116 citations
TL;DR: In this article, a static and dynamic model for amorphous silicon thin-film transistors is presented, based on an assumed exponential distribution of the deep states and the tail states in the energy gap.
Abstract: A static and dynamic model for amorphous silicon thin-film transistors is presented. The theory is based on an assumed exponential distribution of the deep states and the tail states in the energy gap. Expressions are derived that link the density of the localized states and the temperature to the drain current and the distribution of the charge in the transistor channel. In addition the authors take into account parasitic effects such as channel length modulation, off-resistance, drain and source resistances, mobile and free charges in the insulator, surface states, and overlap capacitances. The model is incorporated into the circuit simulation program SPICE. Charge conservation problems are overcome by using a charge-oriented dynamic transistor model. Simulated and measured current-voltage characteristics agree well. A 96-b gate line driver for addressing liquid-crystal displays, which was successfully designed and optimized with the model, is introduced. >
78 citations
TL;DR: In this paper, experimental techniques to characterize typical interconnect discontinuities such as bends and steps, based on time-domain reflection (TDR) measurements, are formulated and characterized in terms of general lumped/distributed circuit models which are compatible with CAD simulation tools such as SPICE.
Abstract: Experimental techniques to characterize typical interconnect discontinuities such as bends and steps, based on time-domain reflection (TDR) measurements, are formulated. These interconnect discontinuities are characterized in terms of general lumped/distributed circuit models which are compatible with CAD simulation tools such as SPICE. The results for the model element values are shown to be consistent with frequency-domain lumped equivalent models for microstrips derived from S-parameter measurements and electromagnetic computations based on the excess inductance and capacitance concepts. The models are also validated by simulating their step response on SPICE and comparing them with the TDR data. >
66 citations
Book•
01 Apr 1992TL;DR: This book illustrates how several drop-in macromodels are interconnected to form an analog phase locked group in the circuit simulation program SPICE.
Abstract: Describes macromodelling with SPICE, the circuit simulation program It covers the applicability of SPICE macromodelling in education and industry 31 "drop-in" models, simulated and verified for use either singly or in groups to perform any analog signal processing function, are provided The book illustrates how several drop-in macromodels are interconnected to form an analog phase locked group
63 citations
TL;DR: In this article, a technique based on additional tracks grounded by vias, with which the cross-talk can be reduced by 50-90%, is presented, with measured results for signals of 50-1000 MHz, and risetimes of 5 ns.
Abstract: In analog and digital electronic systems, cross-talk between tracks on a printed circuit board can degrade the performance of equipment operations. A technique based on additional tracks grounded by vias, with which the cross-talk can be reduced by 50-90%, is presented. The circuit analysis code SPICE is used to analyze a lumped-circuit Tee structure model of three coupled lines. The via discontinuities are modeled in a novel way, which accounts for their transient skin-effect resistance. Both the cross-talk model and the cross-talk reduction technique are validated with measured results for signals of 50-1000 MHz, and risetimes of 5 ns. It is also shown how the far-field radiation from the circuit board is reduced with the introduction of additional grounded tracks. >
58 citations
TL;DR: In this paper, an approach to the modeling of DC-DC converters for SPICE simulation is developed in which the average current in the energy-storage inductor is first simulated in a SPICE subcircuit for both the continuous and discontinuous modes of operation.
Abstract: An approach to the modeling of DC-DC converters for SPICE simulation is developed in which the average current in the energy-storage inductor is first simulated in a SPICE subcircuit for both the continuous and discontinuous modes of operation. The inductor current is then weighted and redistributed to related branches of the circuit to simulate the average input and output currents of the converter. Based on this technique, various converter models, including that of the Cuk converter with coupled inductors, which are valid for both continuous and discontinuous modes of operation, are developed. >
39 citations
TL;DR: The enhanced model (NMOD) exhibits smooth and continuous transitions in the weak to strong inversion region, and in the region between linear and saturation modes of device operation, which improve both the model's current and conductance prediction accuracy, as well as its convergence properties when used in circuit simulation.
Abstract: A MOSFET model optimized for analog circuit simulation is presented and shown to agree with measured device characteristics, especially device output conductance and transconductance, over a wide range of operation. The widely used SPICE Level 3 (MOS3) model equations were utilized as a starting point in the model development process. The enhanced model (NMOD) exhibits smooth and continuous transitions in the weak to strong inversion region, and in the region between linear and saturation modes of device operation. These smooth transitions improve both the model's current and conductance prediction accuracy, as well as its convergence properties when used in circuit simulation. This is made possible because a single current equation is utilized for all regions of device operation. The NMOD model accurately characterizes devices over a wide range of geometries, achieving, for example, 1.3% and 4.2% average errors between measured and model I/sub DS/ and gds characteristics, respectively, for a 20/1.3- mu m p-channel device over a 5-V bias range. >
39 citations
01 Jan 1992
TL;DR: A detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by SPICE LEVEL 3 at peak values and 5% at the average current is presented.
Abstract: Accurate and fast time-domain current waveform simulation is important for the design of reliable CMOS VLSI circuits. A detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by SPICE LEVEL 3 at peak values and 5% at the average current is presented. The current model accounts for short-channel effects, input risetimes, short-circuit and dynamic current, and circuit topology. Moreover, the model produces piecewise linear current waveforms and can be incorporated in any switch-level simulator. Using the models in an event driven simulator, a 3-4 orders of magnitude speedup relative to SPICE LEVEL 3 has been achieved. The results for current waveform accuracy are better than those obtained for previously published methods and in particular for complex CMOS circuits. >
35 citations
TL;DR: In this article, a detailed transient analysis of the MOSFET-BJT combination prevalent in digital BiCMOS gates is presented, which accounts for high-level injection leading to BJT beta rolloff, base pushout leading to f/sub T/rolloff, short-channel behavior of MOS drain current, and parasitic capacitances at the base and output.
Abstract: A detailed transient analysis of the MOSFET-BJT combination prevalent in digital BiCMOS gates is presented. The analysis accounts for high-level injection leading to BJT beta roll-off, base pushout leading to BJT f/sub T/ roll-off, short-channel behavior of the MOS drain current, and parasitic capacitances at the base and output. Based on the transient analysis, a piecewise delay expression is derived that shows excellent agreement with measured gate delay and with SPICE simulated delay. The comparisons are made for a wide range of circuit parameters in the gate, namely, MOSFET/BJT size, load capacitance, and supply voltage for both 1- and 0.6- mu m BiCMOS technologies. The model is used to optimally size gates, and to determine circuit and device design guidelines to minimize the delay degradation at reduced supply. >
29 citations
TL;DR: Based on an approximate solution to the nonlinear current continuity equation in the channel, an analytic non-quasi-static model for long-channel MOSFETs has been derived and implemented in SPICE and includes the large-Signal transient and the small-signal AC analyses.
Abstract: Based on an approximate solution to the nonlinear current continuity equation in the channel, an analytic non-quasi-static model for long-channel MOSFETs has been derived and implemented in SPICE. The model includes the large-signal transient and the small-signal AC analyses, although only the AC model is reported. Excellent agreement in simulation results has been achieved between this work and CODECS (a mixed device and circuit simulator). The CPU time required for this work is about twice as long as that for currently available quasi-static MOSFET models in SPICE. >
28 citations
TL;DR: In this article, the authors describe a parameterized interconnect model library generator that provides VLSI designers with a direct link between numerical method-based capacitance simulators and SPICE-like circuit simulators.
Abstract: The authors describe a parameterized interconnect model library generator that provides VLSI designers with a direct link between numerical method-based capacitance simulators and SPICE-like circuit simulators. As a result, interconnect parasitics are parameterized in a manner similar to the parameterization of transistors in SPICE. Therefore, the effort and time needed by circuit designers or EDA tools to prepare distributed multiline R, C SPICE decks for circuit simulations is drastically reduced. >
TL;DR: In this paper, a method for removing the discontinuity in G/sub ds/ going from the linear region to the saturation region in the MOS level 3 model of SPICE by modifying the channel length modulation expression is described.
Abstract: A method for removing the discontinuity in G/sub ds/ going from the linear region to the saturation region in the MOS level 3 model of SPICE by modifying the channel length modulation expression is described. A detailed analysis of the problem and simulation results before and after the modification are presented. >
TL;DR: In this article, an analytical approach to sizing nFET chains is presented, based on empirical observations of time constants in the classical RC delay model, and on a technology parameter determined from SPICE simulations.
Abstract: An analytical approach to sizing nFET chains is presented. The technique is based on empirical observations of time constants in the classical RC delay model, and on a technology parameter determined from SPICE simulations. The technique allows a delay/area curve to be easily obtained, allowing tradeoff decisions by the circuit designer.
Patent•
25 Sep 1992
TL;DR: In this article, a removable closure body for a spice container is attached to a stationary tubular holder to facilitate one-handed removal of a unit comprising the container and closure body from the holder.
Abstract: A spice container assembly includes a removable closure body for a spice container that is detachably secured to a stationary tubular holder. The spice container in turn, is held by the closure body via a magnet, to facilitate one-handed removal of a unit comprising the spice container and the closure body from the holder. The spice container is retained in or on the closure body by a magnetic force which is used to seal the spice container.
TL;DR: In this paper, the mechanism of duty cycle generation in current mode and average current mode (ACM) PWM convertors is examined and found to be identical except for the functional relationship of the controlling parameters.
Abstract: The mechanism of duty cycle generation in current mode (CM) and average current mode (ACM) PWM convertors is examined and found to be identical except for the functional relationship of the controlling parameters. This result is used to develop a SPICE compatible and topology independent generic current mode (GCM) model.
27 May 1992
TL;DR: The use of advanced devices and emitter-coupled (EC) circuit techniques for implementing ultra-high-speed computer arithmetic is explored and redundant encoding of the input digits and multiple-valued operands are used in the positive-digit and signed-digit number systems.
Abstract: The use of advanced devices and emitter-coupled (EC) circuit techniques for implementing ultra-high-speed computer arithmetic is explored. Redundant encoding of the input digits and multiple-valued operands are used in the positive-digit and signed-digit number systems. Addition in both systems has only three steps and entails no carry propagation chains. Emitter-coupled multivalued logic (MVL) is presented. A novel literal circuit is included. SPICE simulations of AlGaAs/GaAs heterojunction bipolar transistor (HBT) integrated circuits resulted in 1.4-1.6-GHz clock performance estimates of the ECMVL building blocks. Advanced InP-based HBT technology development is proposed to attain 4-10-GHz adder and multiplier performance. Modified circuits using resonant tunneling diodes and transistors are also discussed. >
TL;DR: In this article, a modification of SPICE program, version 2G.6, that allows simulation of networks with multiconductor, lossless transmission lines is dealt with, and the simulator is also useful in determining the upper limit for crosstalk in systems with lossy lines.
Abstract: A modification of SPICE program, version 2G.6, that allows simulation of networks with multiconductor, lossless transmission lines is dealt with. Terminating networks may contain nonlinear active devices defined in the SPICE format. All SPICE 2G.6 transient analysis features and transistor models are supported. The authors describe the computational procedure based on the transmission line equivalent circuit, explain the principle of SPICE implementation, and give examples of application. The simulator developed is also useful in determining the upper limit for crosstalk in systems with lossy lines. However, the simulator underestimates the transmission delays in such cases, and corrections might be needed. Such corrections are relatively easy to do in most practical cases, where DC losses are dominant. >
TL;DR: In this article, an analytical delay model of a CMOS inverter that includes channel-length modulation and source-drain resistance as well as high-field effects is introduced, based on the improved short-channel MOSFET model derived from a quasi-two-dimensional analysis of operation in the saturation region.
Abstract: An analytical delay model of a CMOS inverter that includes channel-length modulation and source-drain resistance as well as high-field effects is introduced. This model is based on the improved short-channel MOSFET model derived from a quasi-two-dimensional analysis of operation in the saturation region. Calculations of the rise, fall, and delay times show good agreement with SPICE MOS level three simulations. >
TL;DR: In this paper, a near-ideal switch model of a thyristor was developed using resistive components, thus eliminating the problems associated with transistor models, and the simulator SPICE 2G.6 was modified and a new input format for the thyristors was implemented.
Abstract: Modifications to the commercially available SPICE 2 program that allow the accurate simulation of thyristor circuits are discussed. A near-ideal switch model of a thyristor is developed using resistive components, thus eliminating the problems associated with transistor models. The simulator SPICE 2G.6 is modified and a new input format for the thyristor is implemented. Examples of simulations with the new model agree closely with theoretical and experimental investigations. >
09 Aug 1992
TL;DR: In this paper, the surface charge is assumed to be lumped into nodes calculated using standard delta depletion (body region) or moderate depletion (drain region) approximations, and an equivalent circuit for the MOSFET model can be derived from the interaction of the internal lumped-charges with the three external terminal voltages.
Abstract: The lumped-charge approach offers a compact, physical power MOSFET model which is equivalent in complexity to the SPICE MOSFET model (level 1) used for low voltage devices. The surface charge is assumed to be lumped into nodes calculated using standard delta depletion (body region) or moderate depletion (drain region) approximations. An equivalent circuit for the MOSFET model can be derived from the interaction of the internal lumped-charges with the three external terminal voltages. The model is implemented in the SABER simulator. Simulated results are in good agreement with measured results. >
10 May 1992
TL;DR: A model for SPICE simulation is proposed which considers several variable temperature influences on transistor parameters as well as a complex thermal network to evaluate the influence of the internal power dependent thermally effected feedback in bipolar transistors.
Abstract: In order to evaluate the influence of the internal power dependent thermally effected feedback in bipolar transistors, a model for SPICE simulation is proposed which considers several variable temperature influences on transistor parameters as well as a complex thermal network. Measurement methods for determination of essential parameter values are suggested. Results of SPICE simulations are presented. >
TL;DR: In this article, a generalized site-binding description is used to model two specific aspects of the ion-selective devices (ISFETs), namely, hysteresis in the response to pH, which is not predicted by the'standard' sitebinding theory.
Abstract: In recent years, much work has been done to characterize ion-selective devices (ISFETs). The response of these devices to pH is commonly explained by considering H+ specific binding sites at the surface of an insulator exposed to an electrolyte. A previous generalized site-binding description is used here to model two specific aspects of the ISFET behaviour, namely: hysteresis in the response to pH, which is not predicted by the 'standard' site-binding theory; partial insensitivity to pH, that is, REFET structures, which are of interest as integrated reference electrodes in differential measurements. The ISFET model is implemented in SPICE and simulation results are given and compared with data reported in the literature.
01 Jan 1992
TL;DR: An RC time-constant based timing simulator is adapted to predict hot-carrier degradation effects in digital CMOS circuits to enable quick characterization of degradation in large circuits.
Abstract: We have adapted an RC time-constant based timing simulator to predict hot-carrier degradation effects in digital CMOS circuits The use of a timing simulator enables a quick characterization of degradation in large circuits The speed-up over SPICE-based simulation can be greater than 3 orders-of-magnitude >
TL;DR: In this article, a simple method is presented to simulate diode selfheating using SPICE without the need for source code modification, and a unique equivalent transformation between temperature-dependent and non-dependent devices is developed.
Abstract: A simple method is presented to simulate diode selfheating using SPICE without the need for source code modification. A unique equivalent transformation between temperature-dependent and nondependent devices is developed. By using a subcircuit to describe this transformation, it is shown that diode selfheating may be readily simulated.
TL;DR: In this article, the linearizing current-mode cell (LCMC) concept is used to design highly linear differential pair transconductors compatible with standard CMOS technology, and the linearity an input voltage range of the proposed circuits are significantly improved over those of the conventional source-coupled differential pair biased by a current sink.
Abstract: Use of the linearising current-mode cell (LCMC) concept is presented to design highly linear differential pair transconductors compatible with standard CMOS technology. The linearity an input voltage range of the proposed circuits are significantly improved over those of the conventional source-coupled differential pair biased by a current sink. The SPICE simulation results show that, for a power supply of +or-5 V, the linearity error is less than 0.2 Omega over +or-4 V differential input range. >
16 Mar 1992
TL;DR: In this paper, a general strategy for direct extraction of MOS transistor DC parameters using only a small number of data points has been developed, which has been implemented for two semi-empirical SPICE mOS transistor models, MOS3 and BSIM.
Abstract: A general strategy for direct extraction of MOS transistor DC parameters using only a small number of data points has been developed. This extraction algorithm has been implemented for two semi-empirical SPICE MOS transistor models, MOS3 and BSIM. Fifteen data points were used to determine the ten MOS3 transistor parameters while 25 data points were used to determine the 20 BSIM parameters. It was possible to obtain good agreement between measured and simulated characteristics. It was also shown that series resistance independent parameters can be extracted with a direct parameter extraction algorithm. >
TL;DR: In this paper, the simulation of two electromagnetic compatibility (EMC) problems, namely crosstalk and field-to-wire coupling, using SPICE, is described, where nonlinearities, protective devices, and even complex circuitry can be included at both ends of the transmission line.
Abstract: The simulation of two electromagnetic compatibility (EMC) problems, namely crosstalk and field-to-wire coupling, using SPICE are described. These modeling techniques for simulation of EMC of multiconductor transmission lines allow calculation in the time domain, as well as the frequency domain. Nonlinearities, protective devices, and even complex circuitry can be included at both ends of the transmission line. Disturbing voltages can also be studied at any node in a susceptor network. The techniques also offer the possibility of including arbitrary sources of radiated disturbances, which could allow the simulation of aperture coupling in an enclosure. >
TL;DR: The effects of parasitic capacitances on distributed high-pass MOSFET filters are investigated and a method for the analysis of distributed MOSfET filters is presented.
Abstract: A method for the analysis of distributed MOSFET filters is presented. The effects of parasitic capacitances on distributed high-pass MOSFET filters are investigated. Three schemes of MOSFET configurations functioning as distributed high-pass filters are presented and analyzed to demonstrate the method and to illustrate the parasitic effects. The analyses are verified by SPICE simulation and the very high frequency numerical model of a MOSFET given by L.J. Pu and Y. Tsividis (1990). >
04 Oct 1992
TL;DR: In this article, the authors describe the design of high-efficiency, electronically commutated, permanent-magnet machine (ECPM) drives based on the finite element/difference method, and the solution of the ensuing differential equations with the Simulation Program with Integrated Circuit Emphasis (SPICE).
Abstract: This paper describes the design of high-efficiency, electronically commutated, permanent-magnet machine (ECPM) drives based on the finite-element/difference method, and the solution of the ensuing differential equations with the Simulation Program with Integrated Circuit Emphasis (SPICE). The permanent-magnet motor model includes the computation of load-dependent components of the motor-equivalent circuit (e.g., induced voltages and inductances). A new SPICE metal-oxide semiconductor field-effect transistor (MOSFET) model reflecting the reverse-recovery current phenomenon-which is very important for the design of variable-speed drives operating in the pulse-width-modulated (PWM) mode-is introduced. Results of this new model are compared with measurements. Since ECPMs lend themselves well to vehicle propulsion due to their inherent high efficiencies at light weight, it is desirable to have a very high output-power-to-weight ratio for such applications. In addition, high ECPM drive efficiencies are important for recovery of the braking energy. >
Book•
27 Feb 1992
TL;DR: Circuit Concepts AC Analysis DC Analysis AC and DC Analysis Transient Analysis AC, DC, and Transient analysis Appendices Index.
Abstract: Circuit Concepts AC Analysis DC Analysis AC and DC Analysis Transient Analysis AC, DC, and Transient Analysis Appendices Index