Showing papers on "Spice published in 1999"

Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing

Abstract: We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of "dominant leakage states" and use state probabilities. Our method achieves speed-ups of 3 to 4 orders of magnitude over exhaustive SPICE simulations while maintaining accuracies within 9% of SPICE. This accurate estimation is used in a new sensitivity-based leakage and performance optimization approach for circuits using dual V/sub t/ processes. In tests on a variety of industrial circuits, this approach was able to obtain 81-100% of the performance achievable with all low V/sub t/ transistors, but with 1/3 to 1/6 the stand-by current.

Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations

Abstract: A 3-D entire SRAM cell, based on a 0.35-/spl mu/m current CMOS technology, is simulated in this work with a DEVICE simulator. The transient current, resulting from a heavy ion strike in the most sensitive region of the cell, is studied as a function of the LET value, the cell layout and the ion penetration depth. A definition of the critical charge is proposed and two new methods are presented to compute this basic amount of charge only using SPICE simulations. Numerical applications are performed with two different generations of submicron CMOS technologies, including the determination of the sensitive thicknesses.

A short-channel DC SPICE model for polysilicon thin-film transistors including temperature effects

Abstract: A semi-empirical analytical model for the DC characteristics of both n- and p-channel polysilicon thin-film transistors is described. The model is suitable for implementation in a SPICE circuit simulator. Our semi-empirical approach results in a physically based model with a minimum of parameters, which are readily related to the device structure and fabrication process. The intrinsic DC model describes all four regimes of operation: leakage, subthreshold, above threshold, and kink. The effects of temperature and channel length are also included in the short-channel model.

SRAM based re-programmable FPGA for space applications

Abstract: An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 /spl mu/m CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor dc-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I/sub CC/) measured indicates a device tolerance of approximately 50 krad(Si).

Macromodeling of single-electron transistors for efficient circuit simulation

Abstract: In this study, the possibility of compact modeling in single-electron circuit simulation has been investigated. It is found that each Coulomb island in single-electron circuits can be treated independently when the interconnections between single-electron transistors are large enough and a quantitative criterion for this condition is given. It is also demonstrated that, in those situations, SPICE macromodeling of single-electron transistors can be used for efficient circuit simulation. The developed macromodel produces simulation results with reasonable accuracy and with orders of magnitude less CPU time than usual Monte Carlo simulations.

Analysis of 3-D interconnect structures with PEEC using SPICE

Abstract: This paper discusses the possibilities of using the circuit simulation program, simulation program with integrated circuit emphasis (SPICE) for the simulation of partial element equivalent circuit (PEEC) models. After an introduction into the PEEC method, the simulation of quasi-stationary models is considered. An enhancement of SPICE is described, allowing the simulation of retarded PEEC models. This enables the computation of electric fields radiated from an interconnection structure. With the modified SPICE simulator it is possible to use existing SPICE models and combine them with full wave PEEC models.

TOM3 capacitance model: linking large- and small-signal MESFET models in SPICE

Abstract: Improved accuracy in the modeled gate capacitance of GaAs metal-semiconductor field-effect transistors (MESFET's) is obtained in SPICE using conservation of charge in an implanted layer. The gate junction creates a natural partition between mobile and fixed channel charges. Relating the gate charge to the channel current creates gate capacitances dependent upon the channel current derivatives linking the small-signal model to the large-signal equations. Results are illustrated using a depletion-mode MESFET.

A physically based analytic model of FET Class-E power amplifiers-designing for maximum PAE

Abstract: In this paper, we present a new Class-E power-amplifier model. Through a physically based analysis, our novel approach yields closed-form expressions for input, output, and dc power. These expressions yield the important figures-of-merit [gain, drain efficiency, and power-added efficiency (PAE)]. Using standard device parameters, design optimization for maximum PAE follows directly from the analysis and applies to bath integrated and discrete transistor implementations. For integrated designs, the optimal FET aspect ratio can be determined, given the design variables of the Class-E output network (output power, frequency, supply voltage, and loaded-Q of the output resonator). In a discrete transistor application, the Class-E network can be optimized for one of the design variables. The detrimental effects of the device parasitics on the amplifier's performance at UHF and microwave frequencies are accounted for in the model and explained in this paper. We verified the validity of the model by comparing our computed values against those from simulations using an optimized 0.5-/spl mu/m CMOS level-3 SPICE model.

Hybrid Circuit Simulator Including a Model for Single Electron Tunneling Devices

Abstract: A hybrid circuit simulator has been developed that incorporates elements of single electron devices into the conventional circuit simulator SPICE (Simulation Program with Integrated Circuit Emphasis) The elements can consist of an arbitrary network of tunnel junctions and capacitors, whose characteristics are calculated using a master equation method By employing the hybrid circuit simulator, we studied a turnstile device feeding the input of a complementary metal-oxide-semiconductor (CMOS) inverter, and were able to more successfully demonstrate the transfer of electrons through the turnstile one by one in SPICE

SPICE macro model for MAGFET and its applications

Abstract: SPICE macro models for magnetic MOSFET (MAGFET) devices in the saturation region are presented. By using the proposed models, the performance of several readout circuits using MAGFET devices could be predictable. In this paper, the magnetic field-to-voltage converter, the magnetically controlled operational-transconductance amplifier, and the magnetically controlled filter and magnetic-operational amplifier using MAGFET devices have been designed, simulated, and tested. The proposed readout circuits using two different CMOS processes have been fabricated. Both simulation and measurement results verify the correctness and flexibility of the proposed SPICE macro models.

A SPICE compatible model of high intensity discharge lamps

Abstract: A SPICE compatible model of high intensity discharge (HID) lamps was developed and verified against experimental results. The model is based on fundamental physical-thermal principles and applies lamp parameters and universal constants. The model was found to faithfully emulate the static and dynamic electrical responses of a high pressure sodium (HPS) lamp under low frequency (50 Hz) and high frequency (30 kHz) excitation.

Spice Products Available to The Planetary Science Community

Abstract: This paper presents the availability of SPICE products to the Planetary Science Community. The topics include: 1) What Are SPICE Data; 2) SPICE File Types; 3) SPICE Software; 4) Examples of What Can Be Computed Using SPICE Data and Software; and 5) SPICE File Avalability.

SPICE modeling of the transient response of irradiated MOSFETs

Abstract: A new SPICE model of irradiated MOSFET taking into account the real response of the four electrodes is proposed. A comparison between SPICE-generated transient response and PISCES device simulation demonstrates the accuracy benefits when used in complex electronic architectures.

Response surface models of electromagnetic devices and their application to design

Abstract: The use of a response surface in the design of an electromagnetic system is described. The surface is generated using a minimum number of points based on the design of experiments. The final surface is integrated in SPICE to provide dynamic performance modeling.

Enhanced heterostructure field effect transistor CAD model suitable for simulation of mixed mode circuits

Abstract: We describe a new enhanced model for deep submicron heterostructure field effect transistors (HFET's) suitable for implementation in computer aided design (CAD) software packages such as SPICE. The model accurately reproduces both above-threshold and subthreshold characteristics of both n- and p-channel deep submicron HFET's over the temperature range 250-450 K. The current-voltage (I-V) characteristics are described by a single, continuous, analytical expression for all regimes of operation, thereby improving convergence. The physics-based model includes effects such as velocity saturation in the channel, drain-induced barrier lowering (DIBL), finite output conductance in saturation, frequency dispersion, and temperature dependence. The output resistance and the transconductance are accurately reproduced, making the model suitable for simulation of mixed mode (digital/analog) circuits. The model has been extensively verified against experimental data for two HFET technologies with gate lengths down to 0.3 /spl mu/m.

Behavioral modeling of charge pump phase locked loops

Abstract: The CP-PLL is a typical mixed signal device; there is no general theory to describe exactly the dynamics of its nonlinear transient. Many models have been presented to model the behavior of the PLL. A discrete linear model, a discrete nonlinear model and an event-driven model of the second order PLL have been proposed. A comparison of these models with a transistor level model shows that the event-driven model is the most accurate. Moreover, the computational effort of these models for a given accuracy is significantly less than a full SPICE simulation.

The development of analog SPICE behavioral model based on IBIS model

Abstract: This paper presents an approach for building an analog SPICE behavioral model based on the information provided by the IBIS model. Such analog SPICE behavioral model can describe both static and dynamic characteristics of I/O buffers. The method to extract dynamic information from IBIS switching waveform VT tables is discussed in detail. Two types of models can be generated depending on the availability of the waveform tables with different load conditions in IBIS data. The influence of waveform table load condition on the validity of the analog SPICE behavioral model is also investigated.

Analysis of the fluxgate response through a simple spice model

Abstract: In this paper, harmonics content of sinusoidal excited fluxgate sensors response is analyzed by means of a simple electrical model developed for SPICE. The model construction is detailed and it is applied to the simplest fluxgate sensor. Well known characteristics of these sensors are confirmed through the simulations, while new useful outcomes are discussed. In particular it is found that the 4th harmonic response has, in analogy to that of the 2nd one, a linear range which is of greater sensitivity independent of the shape of the BH curve. Second and 4th harmonic responses present a negative slope region. Using a previously developed 2nd harmonic fluxgate magnetometer, some preliminary experimental results are obtained confirming the appearance of the negative slope region at its output.

Active substrate coupling noise reduction method for ICs

Abstract: An innovative active noise reduction method for mixed-signal design is presented. This active method which uses a negative feedback technique can reduce the substrate coupling noise by up to 83%. Test results from the MOSIS 1.2 /spl mu/m CMOS process and SPICE simulation are reported.

MOS Transistor Modeling Issues for RF Circuit Design

Abstract: This paper presents the basis of the modeling of the MOS transistor for circuit simulation at radio-frequency (RF). A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. In addition to the intrinsic device and the source and drain series resistance, the model also has a gate resistance, that is fundamental to correctly model the frequency and noise behavior. The subcircuit also includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance y 22. The bias and geometry dependence of all the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y-parameters, the transit frequency and the maximum oscillation frequency are established and compared to measurements made on a 0.25 p m CMOS process. The Y-parameters and transit frequency simulated with this scalable model versus frequency, geometry and bias are in good agreement with measured data The non-quasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced and compared to noise models available in BSIM3v3. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices.

CAD-oriented equivalent circuit modeling of on-chip interconnects for RF integrated circuits in CMOS technology

Abstract: A CAD-oriented modeling methodology for coupled interconnects on lossy substrates in CMOS technology is presented. The modeling technique is based on a quasi-static EM analysis and an equivalent circuit model extraction and model-order reduction procedure. The response of the SPICE compatible equivalent circuit models is in good agreement with the frequency-dependent transmission line characteristics of the interconnects.

Enhanced analog "yields" cost-effective systems-on-chip

Abstract: As device feature sizes of analog MOS circuits are reduced to the deep-submicron ranges, the effect of process variability on circuit performance and reliability is magnified. Yield is becoming more and more critical and statistical methods are required to simulate the effect of process variability to enable circuit designers to "design-in" quality through circuit robustness. More work is needed particularly in the areas of modeling and statistical CAD of submicron, low-voltage mixed-signal ICs. The characterization work needed to tune models to specific VLSI technology, implementation into the SPICE and APLAC simulators, and use in design and optimization of analog and digital VLSI circuits.

A high accuracy power MOSFET SPICE behavioral macromodel including the device self-heating and safe operating area simulation

Abstract: The new analog behavioral modeling features of modern SPICE simulators were used to develop a high accuracy power MOSFET macromodel, that considers the electrothermal processes and simulates the device behavior beyond the safe operating area (SOA) limits. New static equations were implemented with "in-line equation" controlled sources, in order to accurately simulate the device on-state voltage and forward transconductance. The model gives a precise description of the parasitic interelectrode capacitances, that were piecewise-linear approximated with "look-up table" controlled sources. The SOA was simulated by including the device avalanche breakdown and snapback effect. The model's parameters extraction was greatly simplified and the resulting model is portable to all the modern SPICE simulators. The simulations performed for different types of commercial power MOSFETs proved an excellent agreement with the data-sheet characteristics, giving also a reasonable analysis time, with no convergence problems.

A low-voltage CMOS 1-Hz low-pass filter

Abstract: In this paper, we present a technique for the implementation of low cut-off frequency filters based on the use of a second generation current conveyor (CCII) employed as a capacitive multiplier, whose multiplicative effect has been extended successfully at very low frequencies. A first-order 1-Hz low-pass filter was designed to demonstrate the compatibility of the technique with standard IC technologies. The proposed implementation was simulated in SPICE with a 0.5-/spl mu/m CMOS Alcatel Mietec technology and uses a supply voltage as low as 1.5 V. A very good agreement with the theoretical results is found.

Electronically tunable generalized impedance converter structures

Abstract: New generalized impedance converter (GIC) structures realizable with four and six active components (operational amplifiers (OA) and operational tansconductance amplifers (OTA)) in the grounded and floating configurations, respectively, only three passive elements are derived The resulting circuits enable a wide range linear tuning of impedance through the control voltage or current of the ()TA and are expected to find applications in tunable circuits (filter and oscillator for instance) The viability of the proposed structures has been confirmed by SPICE simulation results

An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique

Abstract: This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6 μm CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation.

A novel high-speed flip-flop circuit using RTDs and HEMTs

Abstract: An RTD (resonant tunneling diode)-based flip-flop circuit with a new configuration is proposed. The circuit features an SCFL interface for both input and output, and achieves high-speed operation with a simplified configuration. The circuit consists of only two RTDs and three HEMTs, and works as a delayed flip-flop (D-FF) with return-to-zero (RZ) mode output. 50 Gbit/s operation is confirmed by SPICE simulation for the SCFL-interfaced D-FF with the proposed configuration. A static binary frequency divider (T-FF) is also designed based on the same concept. It is fabricated by InP-based RTD/HEMT integration technology, and its proper operation of up to 15 GHz is confirmed experimentally.

Simulation of single-electron/CMOS hybrid circuits using SPICE macro-modeling

Abstract: Recently, there has been great progress in the fabrication of various nano-devices utilizing silicon ULSI processing techniques [1]. Reliable room temperature operations have been demonstrated in a silicon single-electron quantum-dot transistor [2], a silicon selfassembled quantum-dot transistor [3], and various types of single-electron memory cells [4,5]. However, these single electron or quantum devices usually have extremely poor driving capabilities so that direct application to practical circuits is as yet almost impossible. One possible solution to overcome this problem is to build hybrid circuits consisting of single electron transistors (SETs) and CMOS interfaces [6] and in this case, simultaneous simulations of single electron circuits (SECs) and CMOS circuits are required for efficient circuit design and analysis. Usual SEC simulators such as MOSES [7], SIMON [8], KOSEC [9], and SENECA [10] are not compatible with SPICE and the only way of simultaneous simulation of hybrid circuit is to insert SEC simulation capabilities into SPICE source code. On the other hand, recently developed SPICE macro-modeling technique [9,11] is based on SPICE macro code and can be conveniently used for hybrid circuit simulation without having to modify the SPICE source code. In this paper, the SPICE macro-modeling of SETs has been successfully applied to the simulation of singleelectron/hybrid circuits. Several hybrid circuits such as an SET-NMOS pair and a single electron NOR-gate with CMOS buffers have been simulated and efficient interface characteristics are demonstrated.

A new SPICE behavioral macromodeling method of magnetic components including the self-heating process

Abstract: The aim of this paper is to present a new method of SPICE macromodeling of magnetic components, that is able to simulate both the minor and major hysteresis leaps, and considers as well the self-heating electrothermal effects. The electromagnetic and electrothermal laws are described with "in line equation" controlled sources, that form an electrical equivalent circuit of the global magnetic-electrical-thermal behavior of the magnetic component. The B-H loop is piecewise-linear approximated and therefore any kind of magnetic material can be modeled. The temperature and frequency dependencies of the B-H loop are directly specified in the macromodel with "look-up table" controlled sources. The resulting model is portable in all the modern SPICE simulators that support the behavioral modeling facilities, and it assures a higher accuracy and a better computational efficiency, with no convergence problems.