Showing papers on "Static induction transistor published in 2009"

Junctionless multigate field-effect transistor

Abstract: This paper describes a metal-oxide-semiconductor MOS transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.

Static Random Access Memory (SRAM) Cell and Method for Forming Same

Abstract: An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure.

Field-effect transistor, method for manufacturing field-effect transistor, display device using field-effect transistor, and semiconductor device

Abstract: Provided is a field-effect transistor wherein an oxide film is arranged as a semiconductor layer, the oxide film has a channel portion, a source portion and a drain portion, and compositions of the channel portion, the source portion and the drain portion, excluding oxygen element and an inert gas, are substantially the same.

Semiconductor device and manufacturing methods with using non-planar type of transistors

Abstract: Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A portion of a fin of the non-planar pull-up transistor is electrically connected to a portion of a fin of the non-planar pull-down transistor by an assist-bar. The methods involve forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor and between gate electrodes, and widening a width of the assist-fin to form the assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar.

Double gate and tri-gate transistor formed on a bulk substrate and method for forming the transistor

Abstract: Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas (211D, 211S), the fins (210) and isolation structures (208A) in a self- aligned manner within a bulk semiconductor material. After defining the basic fin structures (210), highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.

Cascode amplifier with protection circuitry

Abstract: A cascode amplifier (300) with protection circuitry is described. In one exemplary design, the amplifier includes multiple branches coupled in parallel (310a, 310b, 310k), with at least one branch being switchable between "on" and "off states. Each switchable branch includes a gain transistor (312) coupled to a cascode transistor (314). The gain transistor (312) amplifies an input signal and provides an amplified signal in the on state and does not amplify the input signal in the off state. The cascode transistor (314) buffers the amplified signal and provides an output signal in the on state. The output signal swing may be split between the gain transistor (312) and the cascode transistor (314) in both the on and off states with the protection circuitry. Each transistor may then observe a fraction of the voltage swing. The voltage splitting in the off state may be achieved by floating the gain transistor (312) and shorting the gate and source of the cascode transistor (314).

Display apparatus and drive control method for the same

Abstract: Supplying first and second measuring voltages to a source terminal of a drive transistor to obtain first and second voltage variations at the source terminal of the drive transistor when a parasitic capacitance of a light emitting element is charged by currents flowed through the drive transistor by the supply of the voltages, obtaining first and second current values of the drive current of the drive transistor based on the first and second voltage variations, obtaining characteristic values of the drive transistor based on the first and second measuring voltages and the first and second current values, and outputting a data signal based on the obtained characteristic values and a drive voltage of the drive transistor corresponding to the amount of emission of the light emitting element to the source terminal of the drive transistor.

Enhancement mode III-nitride switch with increased efficiency and operating frequency

Abstract: According to one exemplary embodiment, an efficient and high speed E-mode III-N/Schottky switch includes a silicon transistor coupled with a D-mode III-nitride device, where the silicon transistor causes the D-mode III-nitride device to operate in an enhancement mode. The E-mode III-N/Schottky switch further includes a Schottky diode coupled across the silicon transistor so as to improve efficiency, recovery time, and speed of the E-mode III-N/Schottky switch. An anode of the Schottky diode can be coupled to a source of the silicon transistor and a cathode of the Schottky diode can be coupled to a drain of the silicon transistor. The Schottky diode can be integrated with the silicon transistor. In one embodiment the III-nitride device is a GaN device.

Inverter, method of operating the same and logic circuit comprising inverter

Abstract: Provided are an inverter, a method of operating the inverter, and a logic circuit including the inverter. The inverter may include a load transistor (T1) and a driving transistor (T2), and at least one of the load transistor and the driving transistor may have a double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter.

Divide-by-two injection-locked ring oscillator circuit

Abstract: A frequency divider involves a plurality of Injection-locked Ring Oscillators (ILRO). A first ILRO includes a pair of cross-coupled N-channel transistors, a pair of load resistors, an integrating capacitor, and a current injection circuit. The drain of each transistor is coupled to the gate of the other transistor. Each load resistor couples the drain of each transistor to a circuit voltage source. The integrating capacitor couples the sources of each transistor. The current injection circuit alternately opens and closes a path from the source of each transistor to circuit ground in response to an oscillatory input signal of a first frequency. In response, the voltage state at the drain of each transistor is alternately latched and toggled, generating a differential pair of oscillating signals frequency divided by two. A first and second ILRO driven in antiphase generate two differential output signals in phase quadrature.

Display device and electronic device including the same

Abstract: It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.

Pixel circuit, display apparatus, and pixel circuit drive control method

Abstract: A pixel circuit including a light emitting element, a driving transistor, connected to the light emitting element, that applies a drive current to the light emitting element, a holding circuit connected to a gate terminal of the driving transistor, and a switching transistor connected between the holding circuit and a data line through which a data signal to be held by the holding circuit flows, in which the driving transistor and the switching transistor are inorganic oxide thin film transistors whose OFF-operation threshold voltage is a negative voltage, and the holding circuit includes a first capacitor element connected between the switching transistor and the gate terminal of the driving transistor, and a second capacitor element connected between a point located between the first capacitor element and the gate terminal of the driving transistor and a voltage source that supplies a negative voltage.

Device Design for a 12.3-Megapixel, Fully Depleted, Back-Illuminated, High-Voltage Compatible Charge-Coupled Device

Abstract: A 12.3-megapixel charge-coupled device (CCD) that can be operated at high substrate-bias voltages has been developed in support of a proposal to study dark energy. The pixel size is 10.5 mum, and the format is 3512 rows by 3508 columns. The CCD is nominally 200 mum thick and is fabricated on high-resistivity n-type silicon that allows for fully depleted operation with the application of a substrate-bias voltage. The CCD is required to have high quantum efficiency (QE) at near-infrared wavelengths, low noise and dark current, and an rms spatial resolution of less than 4 mum. In order to optimize the spatial resolution and QE, requirements that have conflicting dependences on the substrate thickness, it is necessary to operate the CCD at large substrate-bias voltages. In this paper, we describe the features of the CCD, summarize the performance, and discuss in detail the device-design techniques used to realize 200-mum-thick CCDs that can be operated at substrate-bias voltages in excess of 100 V.

Driver circuit, display device, and electronic device

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

Tunneling transistor suitable for low voltage operation

Abstract: Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.

High-Speed Operation of Vertical Type Organic Transistors Utilizing Step-Edge Structures

Abstract: An organic transistor having a novel structure, step-edge vertical-channel organic field-effect transistor (SVC-OFET), with a short channel length has been fabricated by a low-cost self-alignment process. The short channel is formed in the vertical direction along the side wall of a step-edge structure. The SVC-OFET structure also has an advantage in reducing the parasitic capacitance between the gate and drain electrodes. A short channel and reduced capacitance are important properties for a high-speed operation. The cutoff frequency achieved was approximately 900 kHz, which is a very high value for organic transistors.

Techniques for curvature control in power transistor devices

Abstract: Techniques for processing power transistor devices are provided. In one aspect, the curvature of a power transistor device comprising a device film formed on a substrate is controlled by thinning the substrate, the device having an overall residual stress attributable at least in part to the thinning step, and applying a stress compensation layer to a surface of the device film, the stress compensation layer having a tensile stress sufficient to counterbalance at least a portion of the overall residual stress of the device. The resultant power transistor device may be part of an integrated circuit.

A Low Voltage Steep Turn-Off Tunnel Transistor Design

Abstract: —A new tunneling transistor structure is introduced that offers several advantages over prior designs. Notably, tunneling area is substantially increased. Turn on/off swing is improved by engineering doping profile to ensure tunneling initiates in high electric field region. TCAD simulations explore the critical design considerations. The concept of heterojunction tunneling is introduced as a means to achieve low effective band gap and low voltage operation for the design in consideration. I. I NTRODUCTION Increasing power consumption presents a major problem for future ICs. A transistor that can operate below 0.5 V supply is highly desirable. Maintaining large I on /I off ratio at such low V dd is a challenge for MOSFET given the 60 mV/decade subthreshold swing limit. This limit governs the turn off/on of any device based on flow of carriers over an energy barrier. Band-to-band tunneling (BTBT) is one process not subject to this limitation. Researchers have long explored the BTBT transistor [1-2]. However, all have relied on the same basic structure -- the gated PN diode. This conventional structure for an n-type FET is shown in Fig. 1. The location of tunneling is indicated by the arrow at the edge of the source region. The transistor “turns on” when the gate voltage exceeds the overlap voltage, V

Inverter and logic device comprising the same

Abstract: The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor.

Problems of noise modeling in the presence of total current branching in high electron mobility transistor and field-effect transistor channels

Abstract: In the framework of analytical and hydrodynamic models for the description of carrier transport and noise in high electron mobility transistor/field-effect transistor channels the main features of the intrinsic noise of transistors are investigated under continuous branching of the current between channel and gate. It is shown that the current-noise and voltage-noise spectra at the transistor terminals contain an excess noise related to thermal excitation of plasma wave modes in the dielectric layer between the channel and gate. It is found that the set of modes of excited plasma waves can be governed by the external embedding circuits, thus violating a universal description of noise in terms of Norton and Thevenin noise generators.

Organic electroluminescent display device and method of driving the same

Abstract: An organic electroluminescent display device includes an organic electroluminescent diode receiving a driving voltage and a first ground voltage; first and second driving thin film transistors for providing a driving current to the organic electroluminescent diode, each of the first and second driving thin film transistors receiving one of the driving voltage and the first ground voltage; a first switching thin film transistor receiving a data voltage and switched by an nth scan signal to output the data voltage; a second switching thin film transistor switched by a current providing signal to provide the one of the driving voltage and the first ground voltage to the second driving thin film transistor; a third switching thin film transistor receiving a second ground voltage and switched by a selection signal to output the second ground voltage to an output terminal of the first switching thin film transistor; a fourth switching thin film transistor disposed among an output terminal of the second switching thin film transistor, a gate terminal of the first driving thin film transistor and a gate terminal of the second driving thin film transistor and switched by the selection signal; and a first capacitor disposed among the output terminal of the first switching thin film transistor, the gate terminal of the first driving thin film transistor and the gate terminal of the second driving thin film transistor, wherein “n” is a positive integer.

High efficiency CMOS image sensor pixel employing dynamic voltage supply

Abstract: A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.

Solid state imaging device and differential circuit

Abstract: A solid-state imaging device that is configurable into a small size appropriate for expanding dynamic range includes: a photodiode which is a photoelectric conversion unit that generates charge by incident light; a MOS transistor which is connected to the photodiode and transfers the charge; a floating diffusion region which is a first accumulation unit which accumulates the charge via the MOS transistor; a MOS transistor which is a second transfer unit connected to the floating diffusion region and connected in series to the MOS transistor; and a MOS transistor which is an output unit which outputs, via the MOS transistor, a signal voltage in accordance with an amount of the charge.

Transistor, inverter including the same and methods of manufacturing transistor and inverter

Abstract: A transistor, an inverter including the transistor, and methods of manufacturing the inverter and the transistor. A gate insulating layer of the transistor has a charge trap region. A threshold voltage may be moved in a positive (+) direction by trapping charges in the charge trap region. The transistor may be an enhancement mode oxide thin-film transistor (TFT) and may be used as an element of the inverter.

Semiconductor device driving bridge-connected power transistor

Abstract: A semiconductor device includes a low-side circuit, high-side circuit, a virtual ground potential pad, a common ground potential pad and a diode, formed on a semiconductor substrate. The low-side circuit drives a low-side power transistor. The high-side circuit is provided at a high potential region, and drives a high-side power transistor. The virtual ground potential pad is arranged at the high potential region, and coupled to a connection node of both power transistors to supply a virtual ground potential to the high-side circuit. The common ground potential pad supplies a common ground potential to the low-side circuit and high-side circuit. The diode has its cathode connected to the virtual ground potential pad and its anode connected to the common ground potential pad.

Filler circuit cell

Abstract: A filler circuit cell is disclosed. The filler circuit cell includes a decoupled capacitor, a tie low circuit and a tie high circuit. The decoupled capacitor includes a first NMOS transistor and a first PMOS transistor, in which the source/drain of the first NMOS transistor is connected to a second voltage source and the source/drain of the first PMOS transistor is connected to a first voltage source. The tie low circuit includes a second NMOS transistor and a second PMOS transistor and the tie high circuit includes a third NMOS transistor and a third PMOS transistor.

Image sensor and method of driving transfer transistor of image sensor

Abstract: Provided is a 4-transistor CMOS image in which a driving condition or a pixel structure is changed so that a transfer transistor in a pixel operates in a pinch-off condition during reset and transfer operations in order to reduce dark current and fixed-pattern noise caused by a change in an operation condition of the transfer transistor and inter-pixel characteristic discrepancy. The image sensor includes a photosensitive pixel including a transfer transistor for transferring photon-induced charges created in a photodiode; and a voltage control unit for controlling a turn-on voltage applied to a gate of the transfer transistor to be lower than a floating diffusion node voltage plus the threshold voltage of the transfer transistor during a partial or entire section of a turn-on section of the transfer transistor such that the transfer transistor operates in a pseudo pinch-off mode.

Adjusting configuration of a multiple gate transistor by controlling individual fins

Abstract: In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable inter-connect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices.

Symmetric sample and hold over-current sensing method and apparatus

Abstract: An over-current condition is detected in a synchronous DC-DC converter by sampling and holding a measured load current value. The load current is sampled while a low-side transistor is ON and then held when the low-side transistor is OFF. The held value is compared to a threshold value while the low-side transistor is OFF. The comparison occurs during the portion of the cycle when the low-side transistor is OFF so that a comparator has sufficient time in which to detect the over-current condition, even in high duty cycle applications.

ESD Protection using a Capacitivly-Coupled Clamp for Protecting Low-Voltage Core Transistors from High-Voltage Outputs

Abstract: An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor.