Showing papers on "Transistor published in 1971"

Temperature-controlled integrated circuits

Abstract: An integrated circuit comprising several transistors on a chip is maintained at a constant temperature by utilizing certain of the transistors as heating elements and other transistors as temperature sensors in a closed loop feedback network. The remaining transistors-not thus utilized for temperature regulation and sensing are available for use in work circuits where sensitivity to ambient temperature variations or selfheating present design problems.

Microwave transistors: Theory and design

Abstract: Microwave transistors are useful as small-signal amplifiers to 6 GHz and power amplifiers to 4 GHz. Nearly all microwave transistors are of the silicon planar type. Power transistors use three types of geometries--interdigitated, overlay, and mesh--while small-signal transistors use interdigitated only. The general theory of the frequency response of transistors is reviewed, including active and inactive elements. A condensed description of the design and processing steps for a silicon microwave transistor is given. A final section deals with the types of high-frequency measurements used in the design and analysis of transistors.

A fully-decoded 2048-bit electrically-programmable MOS ROM

Abstract: A novel MOS charge storage transistor developed for an electrically-programmable ROM will be described. The memory element is a fully-decoded 2048-bit silicon gate MOS chip that provides access times of 500 ns (dynamic mode) or 800 ns (static mode).

The adjustment of mos transistor threshold voltage by ion implantation

Abstract: Two new techniques have been demonstrated to set the threshold voltage of p‐channel MOS transistors and integrated circuits. Both processes employ ion implantation to alter the doping profile near the Si–SiO2 interface. The first centers the ion distribution at the interface while the second places it well inside the silicon. Thresholds may be modified from enhancement through depletion mode. Either method is compatible with standard MOS processes.

Mosfet logic inverter for integrated circuits

Abstract: The specification discloses a logic inverter comprised of a depletion mode MOSFET used as a resistive load between a drain supply voltage and an output and one or more enhancement mode MOSFET''s connected between output and source supply voltage. The source and gate of the depletion mode device are electrically common, and the gates of the enhancement mode devices form the logic inputs. The use of one enhancement mode device provides a simple inverter, a plurality of enhancement mode devices in parallel form a NOR gate, and a plurality of enhancement mode devices in series form a NAND gate. Combination NOR and NAND GATES may also be formed. The basic inverter circuit is also combined with a push-pull output stage to provide increased speed of operation, particularly at higher drain supply voltages. Still another embodiment utilizes an enhancement mode transistor connected between the depletion mode transistor and the output of the basic inverter stage to provide a disable function in which output drain current is switched off under all logic input conditions.

Noise behavior of Schottky barrier gate field-effect transistors at microwave frequencies

Abstract: The noise behavior of a Schottky barrier gate field-effect transistor is investigated by the use of the noise equivalent circuit. The influence of the carrier velocity saturation is estimated. The noise parameters are calculated by taking into account the influence of parasitic resistances. Measured and calculated noise parameters show good agreement in the frequency range 2-8 GHz.

Semiconductor integrated circuit composed of cascade connection of inverter circuits

Abstract: A semiconductor device composed of cascade connected inverter circuits each comprising a load depletion type MIS transistor and a driving enhancement type MIS transistor. The semiconductor device can be properly operated by setting the threshold voltage of the load MIS transistors at a predetermined value, by selecting the dimensions and materials thereof.

Solid state electronic gauge

Abstract: A gauge comprised of a series of light emitting diodes (LEDs) connected in series to a constant current source with the number of consecutively arranged LEDs which are turned on being indicative of the level of an analog signal. A series of serially connected transistor switches are arranged with one transistor connected in parallel across each light emitting diode, and the analog signal is utilized to selectively and serially turn on the transistor switches to thereby short circuit an equivalent number of the LEDs whereby the magnitude of the analog signal to the switches is inversely proportional to the number of diodes which are turned on.

Monolithic semiconductor circuit for a logic circuit concept of high packing density

Abstract: A monolithic semiconductor circuit comprises a lateral PNP transistor and an inversely operated vertical NPN transistor. The lateral transistor is formed by a pair of mutually spaced P-type regions diffused in an N-type semiconductor body. The collector region has diffused therein a region of N-type and constituting the collector of the vertical transistor. The semiconductor body constitutes the base region of the lateral transistor and the emitter region of the vertical transistor.

Threshold gate circuits employing field-effect transistors

Abstract: A threshold gate comprising a plurality of complementarysymmetry, field-effect transistor inverters, each inverter receiving at its common gate connection a different input signal and each connected at its output terminal to a common circuit output terminal. The gate may have inputs all of the same weight or, with appropriately chosen values of transistor conduction channel impedance or parallel connected inverters, may have inputs of different weight.

One transistor dynamic memory cell

Abstract: A dynamic memory storage cell requires only one field effect transistor to store binary data The data is represented in the form of stored charge utilizing the inherent metal-insulatorsemiconductor capacitance and P-N junction capacitance at the source node of the field-effect transistor An extended portion of the source diffusion in combination with overlying thin oxide and metal layers form a capacitor that further enhances charge storage A matrix of the memory cells form an extremely high density random access memory

A high-performance N-channel MOS-LSI using depletion-type load elements

Abstract: A design approach of the depletion-load inverter is given in which an attempt is made to obtain large noise margins. It is predicted that the circuit will operate with a 10-15 pJ/pF power- delay product at +5-V supply voltage. Some experimental integrated circuits were designed and fabricated by making use of a novel n-channel MOS technology that utilizes both enhancement and depletion-type MOSFET on a chip. A fully decoded transistor- transistor logic (TTL)-compatible READ-ONLY memory was fabricated, resulting in 300 ns total access time at a +5-V single power supply.

Light-emitting diode driver

Abstract: A transistor is driven into conduction by pulses from an external signal source and has an inductance for a collector load. A light-emitting diode (LED) is connected across the inductance and is forward-biased for a short period each time after the transistor ceases conduction. Repetitive pulsing of the LED produces illumination at low-average current consumption.

Modification of channel regions in insulated gate field effect transistors

Abstract: Method of producing channel regions in IGFET''s by implanting ions in the gate region through the gate, the gate of polycrystalline silicon material. The method both produces conducting channel regions and removes conducting channel regions. Enhancement mode and depletion mode transistors can be made. Other devices, such as resistors, can be formed simultaneously or sequentially by the implantation step.

Electrically programmable read only memory array

Abstract: An electrically programmable semiconductor read only memory array which utilizes a floating gate metal-oxide-semiconductor (MOS) device as a storage element is described The floating gate of the device (storage element) may be negatively charged by avalanche injection A field effect transistor is coupled in series with the storage element to form a single memory cell A plurality of cells comprise an array The gate of the field effect transistor is coupled to an X-line of the memory array and one of the other terminals of this transistor, in one embodiment, is coupled to a Y-line of the array The array is electrically programmed by application of information to the X and Y lines of the array

Interface Properties of Al2O3-Ge Structure and Characteristics of Al2O3-Ge MOS Transistors

Abstract: The interface properties of Al2O3-Ge structure formed on germanium wafers by DC reactive sputtering are evaluated. The fast interface states are diminished by subjecting the sample to heat treatment in an inert gas flow. The interface state density is estimated to be typically less than 4×1011 state/cm2-eV from the shift of the flat-band voltage with temperature as originally adopted by Gray and Brown. From the measurement of the parallel conductance of the MOS structure, the electron capture cross section of the trap located at the interface is estimated to be about 0.9×10-17 cm2 using the tunnelling model of Preier, and about 1×10-18 cm2 using the surface potential fluctuation model of Nicollian and Goetzberger. With reactively sputtered Al2O3 films as a gate insulator, n-channel germanium MOS transistors are made with a high effective mobility. The effective mobility is typically more than 2000 cm2/V-sec and the gate threshold voltage is about 1 volt or less.

Current limited battery pack

Abstract: A battery pack includes a resettable protection circuit for limiting the current to a load, which includes a normally nonconductive silicon controlled rectifier and a magnetic reed switch serially connected across a battery. When excessive load current develops, the silicon controlled rectifier is rendered conductive which in turn cuts off a regulating transistor or energizes a relay to prevent current flow to the load. The battery, magnetic reed switch, silicon controlled rectifier and regulating transistor or relay are encased in a sealed container to prevent sparks and arcing and allow usage in a hazardous atmosphere. The silicon controlled rectifier is reset, to allow continued usage of the battery, by actuating the reed switch with an externally supplied magnetic field. Actuation of the reed switch breaks the current path to the silicon controlled rectifier.

Power supply with temperature compensated current foldback

Abstract: A power supply with overload current foldback employs series regulating feedback circuitry for normally controlling the base potential of a series pass transistor. A current limiting transistor selectively connects the pass transistor base and power supply output terminals for reducing pass transistor drive responsive to overload conditions. A temperature responsive load current sensing network is employed to maintain the peak available power supply output current constant, and a constant potential source is utilized for the foldback circuitry to render the foldback characteristic independent of line voltage variations.

Dynamic data storage cell

Abstract: A dynamic data storage cell is disclosed that requires only one insulated gate field effect transistor (IGFET) to store binary data. The drain of the FET is connected to a data input line and data is stored at the source node of the transistor by the inherent capacitance between the source diffusion and the substrate. The capacitance of the source electrode is enhanced by forming a heavily doped layer to underlie a portion of the source diffusion. Using the substrate as circuit ground enables the fabrication of an array of transistors for a random access memory wherein the surface area of the semiconductor chip is minimized.

Solid-state relay using light-emitting diodes

Abstract: A solid-state relay utilizing a light-emitting diode to transmit optical energy steadily to a photo-sensitive solid-state device to control the conductivity of solid -state elements. A relatively low power source of AC or DC can be used to operate photo-sensitive uni-junction transistor or a pair of light-activated silicon-controlled rectifiers.

Shift of the Gate Threshold Voltage of MOS Transistors dne to the Introduction of Shallow Impurities

Abstract: It is possible to shift the gate threshold voltage of MOS transistors with little sacrifice of other device performances by introducing shallow level impurities only into a region near the semiconductor surface under the gate. Some theoretical information is given which may be useful for designing MOS transistors in an attempt to realize such a shift. The effects of the impurity introduction on the characteristics of MOS diode structures are also described.

When are transistors passive

Abstract: The paper presents results on the stability and dynamic behavior under large signal conditions of networks consisting of transistors and sources connected to a linear, passive, memoryless subnetwork. The transistors' model incorporates various nonlinearities. A characteristic common to the main results of the paper is that they relate to properties of the transistors alone and, hence, are independent of the passive part of the network. Sufficient conditions are obtained for asymptotic and bounded input-bounded output stability. The conditions impose restrictions on some of the physical constants of the transistors' model. These conditions have an interesting physical interpretation in terms of temperature differentials in the transistor junctions. In particular, any transistor with the exponential type of static diode characteristic is passive only if the ratio of the junction temperatures lies inside an interval determined by the α's. In the state space of the network there exists a well-defined region R specified by the transistors' model with the property that constant terminal states in R are independent of initial conditions. The region R is in a certain sense maximal.

Carrier multiplication in the pinchoff region of m.o.s. transistors

Abstract: The letter describes a theoretical model for the abnormal current in the substrate of m.o.s. transistors beyond pinchoff. It is shown that this current is due to carrier multiplying by avalanching in the pinchoff region. The corresponding drain conductance is determined. The comparison between experimental and theoretical results is given for several samples.

Experimental evaluation of high energy ion implantation gradients for possible fabrication of a transistor pedestal collector

Abstract: The use of ion accelerators to implant impurities in crystals has become the subject of widespread research. Such studies have been limited mainly to low energies with acceleration voltages of 50 to 500 kilovolts. In this energy range, impurities are implanted into the upper micron or less of the surface. The present work describes certain characteristics of high energy ion implantation. The ions used were boron and phosphorus. They were implanted into silicon with energies of 2 to 4 megavolts. In this energy range, the impurities have a useful positive impurit concentration gradient from the surface. The surface concentration is about 4 × 1016 cm-3, and the peak concentration exceeds 1019 cm-3 depending on dosage. The peak concentration occurs about 2.5 µm deep. After annealing the radiation damage introduced into the semiconductor, it was determined that the surface silicon recovered over 90% of its expected maximum conductivity and mobility. A discussion is given of the concentration gradients required to fabricate a collector pedestal for a high-speed switching transistor, and it is shown that such gradients can be obtained by using high energy ion-implantation. The pedestal may be implanted after the base and emitter diffusions, and annealed at a low temperature, thus keeping a sharp impurity gradient. Also, since it is put into the final epitaxial layer, its vertical position relative to the emitter-base junction will be independent of epitaxial undulations.

Radio frequency transistor package

Abstract: A transistor die is mounted over a pair of mutually opposed ceramic filled microstrip lines having a common ground plane, one of these strip lines being an input strip line and the other being an output strip line. An extention of the common ground plane member extends up through the dielectric fill material of the strip lines into the gap between the mutually opposed ends of the adjacent strip lines to form a common connector terminal. Two sets of leads interconnect the common connector terminal and the input strip line with the base and the emitter electrodes on the transistor die, whereas the collector electrode of the transistor die is electrically and thermally connected to the output strip line.

Multi-emitter power transistor having emitter region arrangement for achieving substantially uniform emitter-base junction temperatures

Abstract: A transistor having a plurality of divided emitter regions. The spacing between adjacent emitter regions at the central portion of the transistor is greater than that between adjacent peripheral emitter regions. This arrangement provides a more uniform distribution of junction temperatures. The structure finds particular utility in power transistors.

Stored charge transistor

Abstract: A stored charge device of the general type designated as an MNOS field-effect transistor, has its operation improved by embedding a thin metal layer between two insulating films used in the transistor. The embedded metal layer technique is also used to provide a two-terminal thin-film stored charge device, consisting of a "metal-insulator-embedded metal-insulator-metal," sandwich structure which can be used in high-density memory arrays.

Method of forming dielectric isolation for high density pedestal semiconductor devices

Abstract: A DIELECTRICALLY ISOLATED SSEMICONDUCTOR DEVICE CAN BE MANUFACTURED, THE STRUCTURE IS USEABLE FOR INTERGRATED CIRCUITS, INCLUDING FIELD EFFECT AND/OR BIPOLAR TRANSISTORS, WHEREIN A SIGNIFICANT SAVINGS IN SURFACE AREA AND REDUCTION IN CAPACITANCES CAN BE OBTAINED OVER PRIOR TECHNIQUES. THE METHOD INVOLVES FORMING A LYYER OF DIELECTRIC MATERIAL UPON A SEMI-CONDUCTOR BODY, HAVING A DIFFUSED REGION WHERE A BIPOLAR DEVICE IS TO BE FORMED, AND THE FORMING AN OPENING IN THE LAYER TO EXPOSE A PART OF THE SURFACE OF THE DIFFUSED REGION OF THE SEMICONDUCTOR BODY. AN EQITAXIAL LAYER OF SILICON IS DEPOSITED ON TOP. SINGLE CRYSTAL SILICON WILL GROW OVER THE EXPOSED SILICON AREA AND IF A DIFFUSED REGION IS PRESENT IN THE SUBSTRATE A PEDESTAL WILL OUTDIFFUSE THROUGH THE SAME AREA FROM THE BURIED DIFFUSED REGION. POLYCRYSTALLINE SILICON WILL GROW ON TOP OF THE DIELECTRIC MATERIAL. THE PEDESTAL IS FORMED IN A SINGLE CRYSTAL EPITAXIAL LAYER OF ANOTHER IMPURITY TYPE. TWO OTHER ACTIVE ELEMENTS OF A BIPOLAR TRANSISTOR, SUCH AS THE EMITTER AND INTRINSIC BASE REGIONS, ARE THEN FORMED IN THE SAME SINGLE CRYSTAL EPITAXIAL LAYER WHILE THE INACTIVE AREA, SUCH AS THE EXTRINSIC BASE, IS FORMED IN POLYCRYSTALLINE SILICON, A REACH THROUGH IS MADE THROUGH THE DIELECTRIC LAYER TO THE THIRD ELEMENT OF THE TRANSISTOR, THAT IS COLLECTOR REGION. D R A W I N G

Solid state relay using photo-coupled isolators

Abstract: A solid state relay coupled to provide current flow to a load from a high voltage source provides high isolation between the relay''s output terminals and an input control gate by means of a photo transistor coupled pair and a photo silicon controlled rectifier coupled pair connected in series circuit for response to the input control gate and by means of an output transistor responsive to the series circuit for providing a current path from the high voltage source through one output terminal, the collector-emitter path of the output transistor and to a load via the other output terminal.