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Boris Hudec
Researcher at National Chiao Tung University
Publications - 51
Citations - 2117
Boris Hudec is an academic researcher from National Chiao Tung University. The author has contributed to research in topics: Atomic layer deposition & Electrode. The author has an hindex of 16, co-authored 45 publications receiving 1341 citations. Previous affiliations of Boris Hudec include Slovak Academy of Sciences.
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Journal ArticleDOI
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices.
TL;DR: This paper proposes a novel ‘Simultaneous Logic in-Memory’ (SLIM) methodology which is complementary to existing LIM approaches in literature and demonstrates novel SLIM bitcells comprising non-filamentary bilayer analog OxRAM devices with NMOS transistors.
Journal ArticleDOI
Recommended Methods to Study Resistive Switching Devices
Mario Lanza,H.-S. Philip Wong,Eric Pop,Daniele Ielmini,Dimitri Strukov,B. C. Regan,Luca Larcher,Marco A. Villena,Jianhua Yang,Ludovic Goux,Attilio Belmonte,Yuchao Yang,Francesco Maria Puglisi,Jinfeng Kang,Blanka Magyari-Köpe,Eilam Yalon,Anthony J. Kenyon,Mark Buckwell,Adnan Mehonic,Alexander L. Shluger,Haitong Li,Tuo-Hung Hou,Boris Hudec,Deji Akinwande,Ruijing Ge,Stefano Ambrogio,Juan Bautista Roldán,Enrique Miranda,Jordi Suñé,Kin Leong Pey,Xing Wu,Nagarajan Raghavan,Ernest Y. Wu,Wei Lu,Gabriele Navarro,Weidong Zhang,Huaqiang Wu,Run-Wei Li,Alexander W. Holleitner,Ursula Wurstbauer,Max C. Lemme,Ming Liu,Shibing Long,Qi Liu,Hangbing Lv,Andrea Padovani,Paolo Pavan,Ilia Valov,Xu Jing,Tingting Han,Kaichen Zhu,Shaochuan Chen,Fei Hui,Yuanyuan Shi +53 more
TL;DR: This manuscript describes the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained.
Journal ArticleDOI
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices
TL;DR: In this paper, the authors proposed a novel "simultaneous logic in-memory" (SLIM) methodology that allows to implement both memory and logic operations simultaneously on the same bitcell in a non-destructive manner without losing the previously stored Memory state.
Journal ArticleDOI
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse
Chih-Cheng Chang,Pin-Chun Chen,Teyuh Chou,I-Ting Wang,Boris Hudec,Che-Chia Chang,Chia-Ming Tsai,Tian-Sheuan Chang,Tuo-Hung Hou +8 more
TL;DR: A two-layer perceptron network is successfully trained online and the classification accuracy of MNIST handwritten digit data set is improved by using 6-/8-b analog synapses, respectively, with extremely high asymmetric nonlinearity.
Journal ArticleDOI
Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication
Hong-Yu Chen,Stefano Brivio,Che Chia Chang,Jacopo Frascaroli,Tuo-Hung Hou,Boris Hudec,Ming Liu,Hangbing Lv,Gabriel Molas,Joon Sohn,Sabina Spiga,Mani Teja Vijjapu,Elisa Vianello,H.-S. Philip Wong +13 more
TL;DR: In this article, the development of resistive switching (RS) device technology including the fundamental physics, material engineering, three-dimensional integration, and bottom-up fabrication is reviewed, and options for 3D memory array architectures are presented for the mass storage application.