Showing papers by "Eric Beyne published in 2020"

Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding

Abstract: This paper presents our approach to hybrid bond scaling to 1μm pitch and recent demonstration results. The direct wafer stacking of two Cu/SiCN surface is realized between slightly protruding Cu nano-pad on one wafer and slightly recessed, but larger, Cu nano-pad on the second wafer. The protruding nano-pad is tailored as smaller than the recessed nano-pad to compensate for the overlay tolerance in the wafer-to-wafer (W2W) bonding. To control the stability and performance of Cu nano-pad integration process, the intensive inline atomic force microscopy (AFM) and surface acoustic microscopy (SAM) characterization is used on various test structures before/after wafer bonding. The surface flatness should be less than 1 nm/μm to ensure void free bonding. This surface planarization is readily achieved for Cu pad densities up to 25%. Finally, we have demonstrated the high yield and low resistance performance across the 300mm wafer for hybrid bond pitches between 5 and 1μm.

Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

Abstract: With each new node, cost and complexity of logic technology increases while being challenged to provide the historical expected improvement in performance. This paper reviews the latest trends and advances in technology to enable logic scaling. Dimensional scaling, enabled by EUV lithography, will continue with advances in multi-patterning. Higher costs of EUV multi-patterning will be mitigated by high (0.55) numerical aperture (NA) EUV simplifying the patterning and potentially leading to higher yield. Logic standard cell scaling below 6-track (6T) with adequate drive current per footprint will require adoption of Gate-All-Around (GAA) device architectures, like nanosheets, along with scaling boosters like buried power rails (BPR) and semi-damascene metal integration scheme with air-gaps. Scaling below 5-track (5T) will require new compact device architectures like complementary FETs (CFETs) and alternate intra-cell interconnect layouts. Slowing SRAM scaling can also benefit from migration to BPR, forksheets and CFETs. Channels formed from 2D materials can theoretically enable gate length (L g ) and contacted poly pitch (CPP) scaling. Several new material innovations will be needed to enable 2D atomic channel transistors. Changing our view from circuits to systems, 3D integration techniques will continue to enable subsystem scaling like cache partitioning of SoCs to improve memory access. Finally, a methodology to estimate the environmental impact of technology scaling choices is proposed.

Entire Domain Basis Function Expansion of the Differential Surface Admittance for Efficient Broadband Characterization of Lossy Interconnects

Abstract: This article presents a full-wave method to characterize lossy conductors in an interconnect setting. To this end, a novel and accurate differential surface admittance operator for cuboids based on entire domain basis functions is formulated. By combining this new operator with the augmented electric field integral equation, a comprehensive broadband characterization is obtained. Compared with the state of the art in differential surface admittance operator modeling, we prove the accuracy and improved speed of the novel formulation. Additional examples support these conclusions by comparing the results with commerical software tools and with measurements.

Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and $\mu$ TSVs

Abstract: In this article, a power delivery network (PDN) modeling framework for backside-PDN configurations is presented. A backside-PDN configuration contains dense microthrough silicon vias ( $\mu $ TSVs) and power/ground metal stack on the backside of the die. This approach separates the PDN from a conventional signaling network of the back-end-of-the-line (BEOL) and improves power integrity and core utilization. We benchmark this technology with conventional front-side BEOL PDN configurations. Owing to the lower resistivity compared with Cu metal lines for advanced technology nodes, we use ruthenium (Ru)-based buried power rail for PDN modeling. Our analysis shows that the steady-state IR-drop reduces by more than $4\times $ in the backside-PDN configuration, and a simultaneous switching noise analysis shows a significant reduction in transient droops. The framework results are validated with a place-and-route (P&R)-based physical implementation flow. We quantify the area improvement in the actual flow and observe 25%–30% improvement in the backside-PDN configuration. From a PDN modeling framework, the PDN results follow a trend similar to the ones obtained from the block-level P&R of the given configurations. Moreover, we investigate the impacts of package-to-die interconnect pitch, metal–insulator–metal cap density, and input pulse on the PDN performance. In addition, we perform thermal modeling to analyze the thermal implications of the backside-PDN configuration. From a thermal modeling perspective, there is negligible influence from a dielectric bonding layer in the backside-PDN configuration.

Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration

Abstract: This paper presents a novel approach for extreme wafer thinning on carrier followed by nano-scale via-last formation in order to achieve sub-500nm pitch interconnects, electrically connecting the backside to the frontside of a device wafer. Indeed, it is expected that most of the 3D System-on-Chip (3D-SOC) integration technology schemes will require a wafer-to-wafer (W2W) bonding approach, combined with via-last TSV (Through Silicon Vias) connections. To reach sub-500nm interconnect pitches, via-last TSV scaling is also expected to follow a similar trend. To do so, a dedicated sub-micron wafer thinning process was developed that enables a very tight thickness control over the entire wafer, with less than 70nm total thickness variation (TTV), and nano-TSV’s were etched using a Bosch process applied to extremely small CD structures (180x250nm top CD). Functional electrical structures have been measured and characterized, showing up to 99% electrical yielding connections between frontside and backside of the device wafers.

Low-Cost Energy-Efficient On-Chip Hotspot Targeted Microjet Cooling for High- Power Electronics

Abstract: This article presents the design, fabrication, experimental characterization, and modeling analysis of the chip-level hotspot targeted liquid impingement jet cooling for high-power electronics. The hotspot targeted jet impingement cooling concept is successfully demonstrated with a chip-level jet impingement cooler with a 1-mm nozzle pitch and 300- $\mu \text{m}$ nozzle diameter fabricated using high-resolution stereolithography (additive manufacturing). The computational fluid dynamics (CFD) modeling and experimental analysis show that the improved hotspot targeted cooler design with fully open outlets can reduce the on-chip temperature difference by 70% compared with the full array cooler at the same pumping power of 0.03 W. The local heat transfer coefficient can achieve $15\times 10^{4}$ W/m2 K with a local flow rate per nozzle of 40 mL/min, requiring a pump power of 0.6 W. The benchmarking study proves that the hotspot targeted cooling is much more energy-efficient than uniform array cooling, with lower temperature difference and lower pump power.

10 and 7 μm Pitch Thermo-compression Solder Joint, Using A Novel Solder Pillar And Metal Spacer Process

Abstract: In this paper, spacer bumps concept is introduced to increase the process window for TCB, lower the sensitivity of electrical yield to bump height variation, maintain the gap between two dies and to prevent too much solder deformation for a test vehicle having multi-diameter bumps from 40um down to 5um pitches. Adding spacer bumps improves the electrical yield dramatically to close to 100% and ensures having good solder joint and IMC formation for both face to face N=2 and back to face N=4 stacks.

3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes

Abstract: We present local & global SRAM macro optimizations for 3nm FinFET and 2nm Nanosheet using Face-to-Face (F2F) and Wafer-to-Wafer (W2W) hybrid bonding at sub 1um pitch. Bonding pad parasitics are measured experimentally to calibrate RC models of the pad used to evaluate 3D-optimized memory macro delays. 3Doptimized macros are designed to reduce the macro external delay by ~50%. With customized SRAM BEOL, performance improvement of up to 70% for larger memories is observed compared with 2D macro. We also show that bit-cell tech-level optimizations have minor impact on the performance of large caches at advanced nodes due to high metal resistance in the macro global routing. Finally, at system-level we partition a L2 data memory (with 3D-optimized macro) from logic showing that the 3D implementation achieves a total of 33% performance gain with respect to a 2D implementation.

Optical Beam-Based Defect Localization Methodologies for Open and Short Failures in Micrometer-Scale 3-D TSV Interconnects

Abstract: We report laser-based fault isolation methodologies for the localization of open and short failures in $1 \times 5\,\,\mu \text{m}$ via-last through-silicon via (TSV) structures for 3-D system-on-chip (SoC) integration. Due to the photosensitive TSV interconnect capacitance, observation of the photocapacitance response enables nondestructive localization of metallization ruptures. A light-induced capacitance alteration (LICA) measurement is demonstrated on an open failed $1 \times 5\,\,\mu \text{m}$ TSV chain structure with a manufacturing defect. We validate our measurements with active voltage contrast imaging in the scanning electron microscope (SEM) and focused-ion beam (FIB) cross sectioning. Second, TSV dielectric defects generating leakage current between TSV and substrate (i.e., short defects) are detected and localized by sensing the laser-induced TSV photocurrent. An optical beam-induced current (OBIC) measurement is demonstrated on electrically overstressed TSV array structures whereby multiple TSVs are configured in a parallel arrangement. By applying a selective substrate removal process, we can expose the full TSV array and perform optical and tilted SEM inspection and reveal pinhole defects in the TSV liner. We further investigate the effect of breakdown energy on the pinhole formation, relate electrical measurements to SEM inspection, and confirm our results by FIB cross sectioning.

Photosensitive polymer reliability for fine pitch RDL applications

Abstract: We present the reliability results obtained on a two-metal level copper RDL patterned on a photosensitive polymer with a target pitch below 4 μm. Our polymer has been submitted to high temperature storage at 150 °C and to temperature humidity stress at 85 °C/85 %RH for 1000 hours. A thermal cycling stress between -50 °C and 125 °C for 1000 cycles was also performed on these samples.Collected electrical data indicate an increase in the copper wires resistivity and via resistance after 1000 hours at 150 °C. Failure analyses performed on the stressed samples reveal the formation of a copper oxide layer on top of the metal lines and at the bottom of the vias resulting from the presence of water at the interface metal/polymer. The presence of moisture inside the polymer is further confirmed by Fourier-transform infrared spectroscopy (FTIR) measurements. These results emphasize the need of a capping layer on top of the metal lines and reiterate the need of a continuous Ti barrier for a reliable process.

Demonstration of a collective hybrid die-to-wafer integration

Abstract: In this paper, a collective hybrid bonding of a die to wafer is demonstrated. The key integration steps such as CMP, wet etch, cleaning, defect metrology, alignment optimization in die to wafer and wafer to wafer bonding tools are discussed in detail. Finally void free Cu to Cu and SiCN-SiCN connection is shown in this paper. Promising electrical yield more than 85% is obtained for the daisy chains containing 219 pad connections.

Introduction of a New Carrier System for Collective Die-to-Wafer Hybrid Bonding and Laser-Assisted Die Transfer

Abstract: Current roadblocks within the collective die-to-wafer bonding flow, limiting die-transfer yield and throughput, are identified and discussed. Based on the obtained assessment a new carrier system is introduced. The use of the ultra-soft and highly-UV-transparent BrewerBOND® C1301 material and its compatibility with BrewerBOND® 701 laser release material, which is coated on top of ultra-thin dies, allows for a room temperature, ultra-low force collective bonding with laser-assisted die transfer sequence.

System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs

Abstract: This paper analyzes the most feasible 3D integration and partitioning scheme for STT-MRAM based caches in an advanced Mobile SoC based on the process demonstration of the first ever functional 3D integrated STT devices. We present 3D partitioning schemes from a design -architecture perspective and Power Performance and Area (PPA) analysis is carried out for the 2D and 3D SoC designs with both SRAM and STT-MRAM caches. Our work shows that the PPA benefits from 3D Memory on Logic partitioning are magnified when it can be exploited to accommodate larger caches in general. We also show that STT-MRAM based 3D partitioned caches can exploit this potential increase in capacity to improve performance even more than SRAM. These 3D Wafer-to-Wafer (W2W) integrated STT-MRAM caches can result in up-to 30% performance improvement at 17% power and 15% footprint reduction for our target SoC.

Thermal, Mechanical and Reliability assessment of Hybrid bonded wafers, bonded at 2.5μm pitch

Abstract: In this paper we address the thermal, mechanical and reliability performance of wafer-to-wafer hybrid bonded CMOS wafers manufactured using standard 65nm technology. Proprietary chip design includes different test structures which enable assessment of hybrid interconnect yield and mechanical induced stress as well as thermal measurements with high spatial resolution. Different tests are conducted to reproduce thermo-mechanical stresses similar to the ones induced in flip-chip assemblies. The study, supported by the finite element simulations includes hot-spot thermal analysis where thermal resistance of hybrid interface is evaluated and the heat spreading effect in both wafers is compared.

Demonstration of Package Level 3D-printed Direct Jet Impingement Cooling applied to High power, Large Die Applications

Abstract: This work presents, for the first time, a package- level, bare die liquid jet impingement 3D polymer microfluidics heatsink fabricated using 3D printing, or additive manufacturing for large die size and high-power applications. The heatsink achieves a chip temperature increase of 17.5°C at a chip power of 285 W for a coolant flow rate of 3.25 LPM, demonstrating that 3D printing enables the design for low-cost, high efficiency direct on-chip microfluidic heatsink with complex internal 3D manifold liquid delivery channels. The measurement results show that the jet impingement cooling performance can be successfully described using a unit cell approach, allowing an easy scaling of the thermal performance for arbitrary die size applications. Long term thermal tests of 1000h show a constant thermal performance and no degradation of the cooler material.

3D Wafer-to-Wafer Bonding Thermal Resistance Comparison: Hybrid Cu/dielectric Bonding versus Dielectric via-last Bonding

Abstract: 3D wafer-to-wafer bonding is a promising fabrication method to create 3D systems with a very high interconnect density. The thermal resistance of the 3D bonding interface can represent a significant contribution of the overall thermal resistance in the 3D chip stack and should therefore be accurately characterized. In this paper, we present the experimental characterization of two different types of 3D wafer-to-wafer bonding: Cu/dielectric hybrid bonding and via-last dielectric bonding. First, we introduce the wafer-level test vehicles and the characterization methodology for the analysis of both bonding interfaces. Then, we estimate the thermal resistance of the bonding interface based on a combination of temperature measurements and finite element thermal simulations. Benchmarking of the measurement results with available literature data on thermal resistance values of 3D interfaces shows that wafer-to-wafer bonding results in a reduction of the bonding layer thermal resistance of 5x and 20x for the hybrid bonding and dielectric bonding respectively, compared to the standard die-to-wafer bonding approach with micro-bumps and underfill.

A Novel Intermetallic Compound Insertion Bonding to Improve Throughput for Sequential 3-D Stacking

Abstract: This article provides a novel 3-D die-to-wafer (D2W) bonding method using intermetallic compound (IMC) layer insertion into a soft Sn bump to generate mechanical connection of two dies, called insertion bonding. A 50% decrease in stacking time can be obtained. Using this process close to a 100% electrical yield of daisy chains containing 800 fine pitch bumps (20 $\mu \text{m}$ ) is achieved. Various challenges for insertion bonding, such as material selection, surface properties of microbumps, bonding optimization, and compatibility with underfill materials, are discussed in this article. In addition, the potential application of IMC insertion bonding to prevent oxide formation for Co-based under bump metallization and as protection layer is explored.

3D Heterogeneous Package Integration of Air/Magnetic Core Inductor: 89%-Effi- ciency Buck Converter with Backside Power Delivery Network

Abstract: We demonstrate a novel concept of integrating $110-\mu \mathrm{m}$ . thick low-resistance high-Q magnetic core inductors in fan-out wafer level packaging (FOWLP). Unlike thin-film magnetic core inductors [1], this solution offers the possibility to embed thick cores to meet power density requirements, allowing for 89% efficiency at 1.2 W /mm2 power density for 2: 1 power conversion with a backside power delivery network (BSPDN) using circular-shaped magnetic inductors.

A novel iso-thermal intermetallic compound insertion bonding approach to improve throughput for 3D die to wafer stacking

Abstract: In this paper, we present a novel approach using preformed IMC layer to mechanically attach two dies at low temperatures and fast time followed by underfilling process. An isothermal bonding profile with a constant arm temperature was developed to save TCB bonding time. At optimized TCB bonding recipe, IMC insertion bonding offers a very short bonding time in the range of 2-5s for each die. The bonding interface temperature is around 150°C. The electrical test results and cross-section images show high stacking yield in the range of 95% and the void-free interface is obtained for a 20μm pitch microbump.

A Novel Resistance Measurement Methodology for $In~Situ$ UBM/Solder Interfacial Reaction Monitoring

Abstract: This article presents a methodology to investigate, in situ , the interfacial solid-state reaction of alternative metallurgical systems, such as Cu/Ni/Sn and Ni/Cu/Sn bumps. The methodology is based on continuous in situ resistance measurements as a function of time and temperature. It allows to extract solid-state interfacial kinetic reaction parameters, such as activation energy and power factor, in a much more precise and faster way than the conventionally used methods. Moreover, the continuous recording of resistance change makes comparing different metallurgical systems easier. This article shows the results obtained using this method for Cu/Ni/Sn and Ni/Cu/Sn.

Process development and characterization of 3D multi-die stacking

Abstract: In this paper the stacking process development and the characterizations of multi-die stacks N=16, which contain 15 thinned top dies on a bottom die, are described. A comparison study between sequential and vertical collective bonding, to see the impact on their characteristics is examined in detail. Also, an in-situ temperature measurement during stacking is performed and a simulation is done to find the proper thermo compression bonding (TCB) profile to stack a large number of dies with good soldering connection also on the bottom die. Multi-die stacks with high alignment accuracy and good electrical yield (e-yield) are made and characterized by cross-section SEM, SAM and X-RAY analysis.

Study on Process Induced out-of-plane deformation for Fan-Out Wafer Level Packaging

Abstract: Fan-Out Wafer-Level-Packaging (FOWLP) has an increased interest because of its lower cost substrate-less and lower footprint driven by the need for higher-density, higher-bandwidth chip-to-chip connections. However, FOWLP process is facing many challenges such as wafer warpage and die shift. Wafer warpage occurs mainly when the temperature changes during processes, due to the mismatch in the coefficient of thermal expansion (CTE) of the constituent materials. Large warpage of the reconstructed wafers leads to difficulties in wafer handling and tool limitations.This study aims to investigate the evolution of wafer-level warpage during FOWLP process. A Finite Element (FE) model considering the viscoelastic behavior of the mold and adhesive materials is presented. The linear viscoelastic behavior of the mold is characterized using nano dynamic mechanical analysis in a frequency domain at different temperatures. The obtained materials properties were validated using FE modelling and warpage measurements of molded wafers during a heating/cooling experiment.

ELD NiB for microbumps passivation and wirebonding

Abstract: In this paper the role of electroless NiB as capping layer for the microbumps in preventing oxidation and improving the solder wetting and wirebonding is discussed. Surface properties of such a layer is analyzed by XPS analysis technique and the mechanical properties such as modulus and hardness are studied using nanoindentation tool. Deposition quality of NiB is investigated using TEM and EDX mapping and at the end the electrical data and cross section SEM images of the stacked samples are discussed when using H 2 plasma cleaning and capping layers for both pre-applied under fill and wafer level UF.

A novel method for characterization of Ultra Low Viscosity NCF layers using TCB for 3D Assembly

Abstract: For die to wafer bonding of high-density interconnects and fine pitch microbumps developing and characterizing suitable underfill materials are required. In general, underfill serve to fill the spaces in-between microbumps for protection and reliability. Among the different types of underfill, Non-Conductive Film (NCF) has the advantages of fillet and volume control, and a built-in flux to aid wetting. However, challenges arise for thin dies and microbumps with fine pitches on film lamination, voiding, transparency, filler percentage, dicing compatibility and most importantly, deformation behavior and possibility to improve solder joint wetting. In a Die-to-Wafer D2W stacking with a Sn solder bump interconnect to Cu UBM, concern is high on the Cu pad oxidation due to the repeated TCB cycles that accelerate oxidation on neighboring dies. Process mitigation is needed to help reducing the oxidation. But even so, an NCF must have good embedded flux activation. Another main factor for an NCF to have efficient TCB process with good solder joint wetting, is the NCF deformation quality in which is a function of its viscosity. This parameter has direct impact on the deformation of solder bumps. High viscosity NCF would be difficult to deform, thus preventing solder contact to pad during TCB reflow temperature. High bond force is required and could lead to reduced alignment accuracy. Filler entrapment is also a subsequent concern for high filler loading, high viscosity NCF. For a low viscous NCF, careful attention in process characterization is needed in TCB with low bond force. Solder joint wetting is a problem with excessive squeeze-out due to fast and instantaneous deformation. With low viscosity, not only the bond force applied should be low, but the deformation behavior should also be understood to enable an effective NCF. We seek to demonstrate in this paper a creative methodology for Non-Conductive Film (NCF) material characterization, considering the factors of NCF viscosity, deformation, and solder squeeze-out. Characterizing NCF viscosity at fast TCB profiles is challenging considering deformation behavior of both the NCF itself and the solder bumps that shaped the solder squeeze-out and wetting. Furthermore, in this paper we use TCB tool position tracking to define the deformation curve of NCF film as a function of temperature and time at very fast profile of TCB. We use material viscosity curve as reference in relation to the actual deformation, and predict dynamic deformation based on Reynold’s equation within TCB profile duration. The experiments were performed with different heating ramp rates at target above Sn reflow of ~250C interface temperature. The deformation analysis is not limited to thin film sandwiched between parallel plates. Deformation test was performed on chips with and without microbumps and with rigid flat glass surface and its combinations. Deformation of underfill is recorded in the readout of TCB tool. As validation, we applied the optimized TCB process (force, temperature, and ramp rate) on a test vehicle with 20 and 40um pitch daisy chains and obtained close to 95% electrical yield with good joint and IMC formation. The cross-section SEM images show good wetting, revealing good activation of built-in flux when the optimized TCB profile was used.

Evaluation of UBM oxidation through air exposure and heating and effectiveness of wet and plasma cleaning on solder joint formation during TCB

Abstract: In 3D stacking chips, interconnections play an important role and selection of right materials is very significant. In this paper, a systematic study is done to characterize metal oxide growth rate with time and temperature for three most used UBM (under bump metallization) materials i.e. copper, cobalt, and nickel for the interconnections. Furthermore, effectiveness of two cleaning techniques such as wet cleaning and plasma cleaning before TCB (thermo compression bonding) process is investigated. As the metal oxidation, depending on air exposure through time, needs a quick and accurate evaluation, SE (spectroscopic ellipsometry) is employed to measure optical phase quantity (Delta) and thickness. To monitor grain size evolution and measure roughness of the sample surface, AFM (Atomic Force Microscopy) is used. Moreover, wettability of the materials surface, as a key factor in bonding, is measured by Contact Angle tool. As copper is considered a main material for UBM, TOF-SIMS (time of flight second ion mass spectroscopy) as well as XRD (X-ray diffraction) techniques were selected to investigate oxidation concentration along depth profile and oxide phase of the surfaces for the samples respectively and cross section of the oxide layer is observed through SEM.

Modeling of Buck Converter with 3D Air-Core Inductor

Abstract: A high-efficiency and high-power density buck converter is presented in this work with in-package 3D air-core inductor (150 µm thick). To optimize the system efficiency at targeted power density, an analytical model for both the 3D inductor and power switches is developed. Compared to 3D EM simulation, the proposed inductor model has maximum modeling error of 12% and 25% for the inductance and resistance calculations respectively. With the proposed design methodology, an inductor Q factor up to 35 @ 300 MHz is achieved. 1/2-ratio buck converter can reach 90% efficiency @ 1–5W/mm2 based on three optimized inductor designs, with V OUT ranging from 0.7 V to 0.9 V and based on 28 nm CMOS.