Showing papers by "Gerald Lucovsky published in 1999"

Bonding constraints and defect formation at interfaces between crystalline silicon and advanced single layer and composite gate dielectrics

Abstract: An increasingly important issue in semiconductor device physics is understanding of how departures from ideal bonding at silicon–dielectric interfaces generate electrically active defects that limit performance and reliability Building on previously established criteria for formation of low defect density glasses, constraint theory is extended to crystalline silicon–dielectric interfaces that go beyond Si–SiO2 through development of a model that quantifies average bonding coordination at these interfaces This extension is validated by application to interfaces between Si and stacked silicon oxide/nitride dielectrics demonstrating that as in bulk glasses and thin films, an average coordination, Nav, greater than three yields increasing defective interfaces

Band offsets for ultrathin SiO2 and Si3N4 films on Si(111) and Si(100) from photoemission spectroscopy

Abstract: High resolution soft x-ray photoelectron spectroscopy with synchrotron radiation is used to study the interfaces of SiO2/Si(111), SiO2/Si(100), Si(111)/Si3N4, and SiO2/Si3N4 for device-quality ultrathin gate oxides and nitrides. The thin oxides and nitrides were grown by remote plasma deposition at a temperature of 300 °C. Aftergrowth samples were further processed by rapid thermal annealing for 30 s at various temperatures from 700 to 950 °C. The Si(111)/Si3N4 samples were air exposed and formed a thin ∼6 A SiO2 layer with a Si(2p) core-level shift of 3.9 eV, thus allowing us to study both the Si(111)/Si3N4 and SiO2/Si3N4 interfaces with a single type of sample. We obtain band offsets of 4.54±0.06 eV for SiO2/Si(111) and 4.35±0.06 eV for SiO2/Si(100) with film thicknesses in the range 8–12 A. The Si(111)/Si3N4 nitrides show 1.78±0.09 eV valence-band offset for 15–21 A films. This value agrees using the additivity relationship with our independent photoemission measurements of the nitride–oxide valence-ba...

Structure of ultrathin SiO2/Si(111) interfaces studied by photoelectron spectroscopy

Abstract: Device-grade ultrathin (9–22 A) films of silicon dioxide, prepared from crystalline silicon by remote-plasma oxidation, are studied by soft x-ray photoelectron spectroscopy (SXPS). The 2p core-level spectra for silicon show evidence of five distinct states of Si, attributable to the five oxidation states of silicon between Si0 (the Si substrate) and Si4+ (the thin SiO2 film). The relative binding energy shifts for peaks Si1+ through Si4+ (with respect to Si0) are in agreement with earlier work. The relatively weaker signals found for the three intermediate states (I1, I2, and I3) are attributed to silicon atoms at the abrupt interface between the thin SiO2 film and substrate. Estimates of the interface state density from these interface signals agree with the values reported earlier of ∼2 monolayers (ML). The position and intensity of the five peaks are measured as a function of post-growth annealing temperature, crystal orientation, and exposure to He/N2 plasma. We find that annealing produces more abrup...

Ultrathin nitrided gate dielectrics: plasma processing, chemical characterization, performance, and reliability

Abstract: The incorporation of nitrogen (N) atoms into ultrathin gate dielectrics 1) at monolayer levels at Si-SiO2 interfaces reduces tunneling current and defect generation; 2) in bulk nitrides, as in oxide-nitride-oxide (ONO) or oxide-nitride (ON) composite structures, allows the use of physically thicker films without reduced capacitance compared to single-layer oxides; and 3) in nitrided layers at the polycrystalline Si-dielectric interface or in ON dielectrics reduces boron (B) atom out-diffusion from heavily doped p+ polycrystalline silicon gate electrodes into oxide gate dielectrics The results presented in this review demonstrate that N atoms can be selectively and independently incorporated into different parts of the gate dielectric by low-temperature remote-plasma-assisted processing When combined with low-thermal-budget rapid thermal annealing, this yields ultrathin gate dielectrics with performance and reliability which generally exceeds that of single-layer thermally grown oxides The devices addressed in this paper include n-MOS and p-MOS field-effect transistors (FETs) with oxide-equivalent thicknesses of less than 2 nm

Monolayer-level controlled incorporation of nitrogen in ultrathin gate dielectrics using remote plasma processing: Formation of stacked “N–O–N” gate dielectrics

Abstract: A low thermal budget approach to monolayer-level controlled incorporation of nitrogen in ultrathin gate dielectrics using 300 °C, remote plasma processing is discussed. Incorporation of approximately 1 ML of nitrogen at the Si–SiO2 interface in an “N–O” structure has been achieved by remote plasma-assisted oxidation of the Si surface followed by N2/He remote plasma nitridation, each at a process pressure of 0.3 Torr. The interface nitridation reduces direct and Fowler–Nordheim tunneling by at least one order of magnitude, independent of film thickness. Incorporation of nitrogen at the top surface of the oxide in a concentration equivalent to about 1–2 molecular layers of silicon nitride in an “O–N” structure has been accomplished by N2/He remote plasma nitridation at 300 °C, but at a reduced process pressure of 0.1 Torr. Top surface nitridation has been shown to prevent boron diffusion out of p+ poly-Si gate electrodes during high-temperature activation anneals, e.g., at 1000 °C. Combining interfacial and...

Monolayer-level controlled incorporation of nitrogen at Si–SiO2 interfaces using remote plasma processing

Abstract: We demonstrate three different ways to incorporate nitrogen at Si–SiO2 interfaces: (i) an O2/He plasma oxidation of the Si surface followed by an N2/He plasma nitridation, (ii) an N2/He plasma nitridation of the Si surface, and (iii) a Si3N4 film deposition on to the Si surface. The two-step interface formation, the O2/He plasma oxidation followed by the N2/He plasma nitridation, is shown to yield significantly better interface device properties than the other two approaches. These differences in interface properties are explained by an application of constraint theory based on comparisons of the average bonding coordination of the dielectric layer at the interface with the Si substrate.

Interfacial properties of ultrathin pure silicon nitride formed by remote plasma enhanced chemical vapor deposition

Abstract: This article addresses the electrical properties of interfaces between n- and p-type Si and remote plasma-deposited Si3N4, which are of interest in aggressively scaled advanced CMOSFETs. The nitride films of this article display excellent electrical properties when implemented into stacked oxide/nitride dielectrics in both NMOSFETs and PMOSFETs with oxide, or nitrided oxide interfaces. The same nitride layers deposited directly onto clean Si surfaces display degraded electrical properties with respect to devices with oxide, or nitrided oxide interfaces. PMOS interfaces are significantly more degraded than n-type metal–oxide semiconductors interfaces indicating a relatively high density of donor-like interface traps that inhibit channel formation.

Bonding constraint-induced defect formation at Si-dielectric interfaces and internal interfaces in dual-layer gate dielectrics

Abstract: As aggressive scaling of integrated circuits continues into the next century, insulators with dielectric constants higher than SiO2 with different local bonding arrangements will be required to increase gate dielectric capacitance in field effect transistor devices. An important issue in semiconductor device physics is determining whether differences between the bonding at (i) Si–SiO2 interfaces and (ii) interfaces between crystalline Si and alternative gate dielectric materials will result in increased densities of electrically active defects at the alternative dielectric interfaces, thereby limiting targeted levels of performance and reliability. In particular, it is important to understand from a chemical bonding perspective why Si–SiO2 interfaces display both low defect densities and high reliability, while other interfaces such as Si–Si3N4 with similar bonding chemistry, display defect densities that are at least two orders of magnitude higher. Building on previously established criteria for formatio...

Thermochemical stability of silicon–oxygen–carbon alloy thin films: A model system for chemical and structural relaxation at SiC–SiO2 interfaces

Abstract: Alloy thin films of hydrogenated silicon–oxygen–carbon (Si,C)Ox x<2, were deposited and analyzed in terms of changes in structure and bonding as a function of rapid thermal annealing between 600 and 1100 °C using a combination of Fourier transform infrared spectroscopy, Raman scattering and high-resolution transmission electron microscopy. Results showed that three structural/chemical transformations took place upon annealing. The initial reaction (600–800 °C) involved the loss of hydrogen bonded to both silicon and carbon. At intermediate temperatures (900–1000 °C) a Si–O–C type bond was observed to form, and subsequently disappear after annealing to 1050 °C. The formation of ordered amorphous-SiC regions, nanocrystalline-Si regions, and stoichiometric, thermally relaxed SiO2 accompanied the disappearance of the Si–O–C bond at the 1050 °C annealing temperature. Using this alloy as a model system, important information is obtained for optimized processing of SiC–SiO2 interfaces for device applications.

Silicon oxide/silicon nitride dual-layer films: a stacked gate dielectric for the 21st century

Abstract: Incorporation of nitrogen atoms into ultra thin (<0.3 nm) gate dielectrics (i) reduces defect generation at the Si-SiO 2 interface, (ii) allows use of physically thicker dielectrics when incorporated into oxide-nitride stacked gate dielectrics, and (iii) prevents boron atom transport out of heavily doped p + polycrystalline silicon gate electrodes when nitrided layers are incorporated at the polycrystalline Si-dielectric interface. I demonstrate that nitrogen atoms can be selectively and independently incorporated into different parts of the gate dielectric structure by low-temperature (∼300°C) remote plasma assisted processing followed by low-thermal budget rapid thermal annealing (RTA) yielding state of the art field effect transistors with oxide equivalent thicknesses less than 2 nm.

Suppression of boron transport out of p+ polycrystalline silicon at polycrystalline silicon dielectric interfaces

Abstract: The transport of B atoms out of p+ polycrystalline silicon (poly-Si) gate electrodes through SiO2 gate oxides to the Si–SiO2 interface during dopant activation anneals degrades performance and reliability of hole-conducting (p-channel) field effect transistors. This article studies the suppression of B atom transport by using remote plasma processing to form ultrathin Si3N4 and silicon oxynitride diffusion barrier layers between p+ poly-Si gate electrodes and SiO2 gate dielectrics. Suppression of B atom transport has been monitored through electrical measurements, demonstrating that ∼0.8 nm of Si3N4, equivalent to a N areal density of ∼4.5×1015 atoms cm−2, is sufficient to effectively suppress B out diffusion during aggressive anneals of ∼1 min at 1000 °C. The suppression and transport mechanisms in nitrides, oxides, and oxynitrides have been studied by varying the N atom areal density by alloying. Quantum chemistry calculations suggest that B transport occurs through the formation of donor-acceptor pair ...

Charge Redistribution at GaN–Ga2O3 Interfaces: A Microscopic Mechanism for Low Defect Density Interfaces in Remote Plasma Processed MOS Devices Prepared on Polar GaN Faces

Abstract: Interfacial defect densities, typically two orders of magnitude lower than those usually obtained at [III–V]-dielectric interfaces, have been demonstrated for GaN capacitors and field effect transistors (FETs). Separate and independently controlled interface formation and film deposition by remote plasma-assisted processing steps performed at 300 °C were employed. The interfacial oxide is Ga2O3, and the deposited gate dielectric is SiO2. Models for the chemical bonding at the GaN–Ga2O3 interface and at the internal dielectric Ga2O3–SiO2 are presented. The most important aspect of the interface formation involves a redistribution of electrons in the surface atom dangling bonds of the GaN polar face that promotes formation of two-electron bonds with the interfacial dielectric.

Reaction/annealing pathways for forming ultrathin silicon nitride films for composite oxide-nitride gate dielectrics with nitrided crystalline silicon-dielectric interfaces for application in advanced complementary metal-oxide-semiconductor devices

Abstract: Aggressive scaling of complementary metal–oxide–semiconductor (CMOS) devices requires gate dielectrics with an oxide equivalent thickness, tox,eq∼1 nm or less by the product introduction year 2012. Direct tunneling presents a significant performance limitation in field-effect transistors (FETs) with homogeneous oxide gate dielectrics <1.7 nm. Boron diffusion from p+ poly-Si gate electrodes in p-channel FETs leads to additional electrical problems for oxide thicknesses <3 nm. Interfacial nitridation improves reliability in n-channel FETs; however, by itself, it is not effective in p-type metal–oxide–semiconductor FETs due to boron pileup at the Si–dielectric interface. Proposed solutions include top-oxide surface nitridation and the integration of composite oxide–nitride dielectrics into CMOS devices. This review discusses the integration of hydrogenated silicon nitride films, prepared by remote plasma-enhanced chemical-vapor deposition, into electrical devices with composite oxide–nitride (ON) gate dielec...

Time dependent dielectric wearout (TDDW) technique for reliability of ultrathin gate oxides

Abstract: The degradation of ultrathin oxides is measured and characterized by the dual voltage time dependent dielectric wearout (TDDW) technique. Compared to the conventional time-dependent dielectric breakdown (TDDB) technique, a distinct breakdown can be determined at the operating voltage I-t curve. A noisy, soft prebreakdown effect occurs for 1.8-2.7 nm ultrathin oxides at earlier stress times. The different stages of wearout of 1.8-2.7 nm oxides are discussed. The wearout of oxide is defined when the gate current reaches a critical current density at the circuit operating voltage. Devices still function after the soft breakdowns occur, but are not functional after the sharp breakdown. However, application of the E model to project the dielectric lifetime shows that this is more than 20 y for thermal oxides in the ultrathin regime down to 1.8 nm.

Stability of Si–O–F low-K dielectrics: attack by water molecules as function of near-neighbor Si–F bonding arrangements

Abstract: Ab initio configuration interaction calculations have been previously used to account for the relatively large decreases (∼20%) in the static dielectric constant of Si–O–F alloys with for F alloy atom concentrations of ∼10 at.%. This study addresses the stability of these alloy films with respect to attack of Si–F bonds by water molecules. The present calculations show that the reactions of isolated Si–F with water molecules differ from the reactions of nearest-neighbor Si–F groups with water molecules. For example, hydrogen attachment of water to two Si–F groups has a bonding energy of ∼0.5 eV, whereas attachment to an isolated Si–F group has an attachment energy smaller by more than a factor of 6. Combining these calculations for interactions with H 2 O with a statistical model of bonding in the alloy films, an upper limit for chemically stable F-corporation has been determined to be ∼11 at.% F, which corresponds to the static dielectric constant of ∼3.3.

Cathodoluminescence spectroscopy of nitrided SiO2–Si interfaces

Abstract: We use cathodoluminescence spectroscopy (CLS) to investigate the electronic states of ultrathin gate dielectrics with nitrided SiO2–Si interfaces, known to improve reliability in advanced complementary metal–oxide–semiconductor devices. The 5 nm thick films investigated were: (i) as-deposited (at 300 °C) structures, (ii) 400 °C hydrogen anneal, (iii) 900 °C rapid thermal anneal (RTA), and (iv) a combination of both anneals. CLS emission energies and intensities versus excitation energy were essentially unchanged for the as-deposited interface compared to non-nitrided plasma-processed interfaces. In the near-infrared, features appear at 0.8 and 1.0 eV, with the 1.0 eV peak Si substrate intensity increasing with increasing depth. From depth variation measurements at higher photon energy, a 3.4 eV peak is also shown to arise from the Si substrate, and a 2.7 eV feature is shown to come from the interface region. After hydrogenation, the CLS is essentially the same as for non-nitrided interfaces, except for an...

Binary non-crystalline oxide analogs of silicon dioxide for use in gate dielectrics

Abstract: The invention generally relates to oxides that may be used in conjunction with integrated circuit devices. The oxides are non-crystalline. The oxides are represented by the formula: ABO4, wherein A is an element selected form Group IIIA of the periodic table; and B is an element selected form Group VB of the periodic table. The oxides may be employed in field effect transistors as tin gate insulating layers having high dielectric constants.

Why SiN x :H is the Preferred Gate Dielectric for Amorphous Si Thin Film Transistors (TFTS) and SiO 2 is the Preferred Gate Dielectric for Polycrystalline Si TFT s

Abstract: Constraint theory developed for bulk glasses and recently applied to thin films and single crystalline Si (C-Si) dielectric interfaces is extended in this paper to a-Si:H and polycrystalline-Si (poly-Si) dielectric interfaces in TFTs where it provides guidelines for device optimization. The constraining effects of network bonding forces are a linear function of the average bonding coordination, Nav. Nav ~ 3 separates low-defect density networks as in Si02 (Nav =2.67), from highly-defective networks such as non-hydrogenated Si3N4 (Nay = 3.43). Nay ~ 3 also separates device-quality from highly-defective Si-dielectric interfaces. These criteria are applied to Si-Si02 and Si-SiNx:H interfaces that are integral components of TFT devices.

Aggressively Scaled P-Channel Mosfets With Stacked Nitride-Oxide-Nitride, N/O/N, Gate Dielectrics

Abstract: Ultrathin (tox, eq < 2.0 nm) Si3N4/SiO2(hereafter N/O) gate dielectrics with improved interface characteristics compared to devices with thermal oxides have been formed by remote plasma enhanced CVD of Si3N4onto oxides. If the Si-Si02 interface is intentionally nitrided prior to the Si3N4deposition, the increased physical thickness of the N/O stack combined with the interfacial nitridation reduces the direct tunneling current by more than two orders of magnitude. The ensuing device structure can then be characterized as N/O/N. The top nitride layer is also an effective boron diffusion barrier improving short channel characteristics in p+-poly PMOSFETs. In addition, nitrogen can also be transported to the silicon/dielectric interface during post-deposition RTAs, and this reduces degradation of transconductance during hot carrier stressing.

The Effects of Interfacial Suboxide Transition Regions on Direct Tunneling in Oxide and Stacked Oxide-Nitride Gate Dielectrics

Abstract: Mesarjian et al. were the first to recognize the effects of suboxide interfacial transition regions at Si-SiO2 interfaces on tunneling oscillations in the Fowler-Nordheim regime. This paper extends these ideas to the direct tunneling regime and focuses on differences in interfacial transition regions between Si-SO2 interfaces with, and without monolayer level interface nitridation. Tunneling currents in both the direct and Fowler-Nordheim tunneling regimes are reduced by monolayer level interface nitridation for PMOS and NMOS devices with the same oxide-equivalent thickness. This paper develops a modified barrier layer model based on analysis of XPS results that accounts for these reductions in current in the direct tunneling regime.