Showing papers by "Robert A. Reed published in 2014"

Impact of Technology Scaling on SRAM Soft Error Rates

Abstract: Soft error rates for triple-well and dual-well SRAM circuits over the past few technology generations have shown an apparently inconsistent behavior. This work compares the heavy-ion induced upset cross-section in 28, 40, and 65 nm dual- and triple-well SRAMs over a wide range of particle LETs. Similar experiments on identical layouts for all these technologies along with 3-D TCAD simulations are used to identify the dominant mechanisms for single-event upsets. Results demonstrate that the well-engineering strongly influence the single-event response of SRAMs. Layout also plays an important role and the combined effects of well-engineering and layout determine the soft-error sensitivity of SRAMs fabricated in advanced technology nodes.

Geometry Dependence of Total-Dose Effects in Bulk FinFETs

Abstract: The total ionizing dose (TID) response of bulk FinFETs is investigated for various geometry variations, such as fin width, channel length, and fin pitch. The buildup of oxide-trapped charge in the shallow trench isolation turns on a parasitic transistor, leading to increased leakage current (higher IOFF.) The TID-induced degradation increases with decreasing fin width. Transistors with longer channels degrade less than those with shorter channels. Transistors with large fin pitch degrade more, compared to those with narrow fin pitch. TCAD simulations are used to analyze the buildup of trapped charge in the trench isolation oxide and its impact on the increase in leakage current. The strong influence of charge in the STI in narrow-fin transistors induces a parasitic leakage current path between the source and the drain, while in wide-fin devices, for the same amount of trapped charge in the isolation oxide, the subsurface leakage path is less effective.

Hardness Assurance for Proton Direct Ionization-Induced SEEs Using a High-Energy Proton Beam

Abstract: The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data from 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. As a result, we show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI.

Bias Dependence of Total Ionizing Dose Effects in SiGe-MOS FinFETs

Abstract: The total ionizing dose (TID) response of double-gate SiGe- SiO 2 /HfO 2 pMOS FinFET devices is investigated under different device bias conditions. Negative bias irradiation leads to the worst-case degradation due to increased hole trapping in the HfO 2 layer, in contrast to what is typically observed for devices with SiO 2 or HfO 2 gate dielectrics. This occurs in the devices because radiation-induced holes that are generated in the SiO 2 interfacial layer can transport and become trapped in the HfO 2 under negative bias, leading to a more negative threshold voltage shift than observed at 0 V bias. Similarly, radiation-induced electrons that are generated in the SiO 2 interfacial layer can transport into the HfO 2 and become trapped under positive bias, leading to a more positive threshold voltage shift than observed at 0 V bias.

Bias Dependence of Total Ionizing Dose Effects in SiGe

Abstract: The total ionizing dose (TID) response of double-gate SiGe- MOS FinFET devices is investigated under different device bias conditions. Negative bias irradiation leads to the worst-case degradation due to increased hole trapping in the layer, in contrast to what is typically observed for devices with or gate dielectrics. This occurs in the devices be- cause radiation-induced holes that are generated in the inter- facial layer can transport and become trapped in the under negative bias, leading to a more negative threshold voltage shift than observed at 0 V bias. Similarly, radiation-induced electrons that are generated in the interfacial layer can transport into the and become trapped under positive bias, leading to a more positive threshold voltage shift than observed at 0 V bias. Index Terms—Double-gate FinFETs, ,S iGe, threshold voltage shift, total ionizing dose.

Single- and Multiple-Event Induced Upsets in ${\rm HfO}_2/{\rm Hf}$ 1T1R RRAM

Abstract: Single-event upsets in 1T1R Resistive Random Access Memory (RRAM) structures are experimentally demonstrated by generating current transients in the access transistors of the memory cells. The relationship between the single-event upset threshold of the RRAM and the applied voltage is exponential, which is verified using TPA laser analysis and heavy-ion irradiation. Multiple-Event Upsets (MEUs) also occur, where individual ions incrementally change the RRAM's resistance until their cumulative effect causes an upset. Single-event models are presented that allow direct correlation of the voltage across the RRAM, caused by the ion-generated current transient, and the change in RRAM resistance. The RRAM is vulnerable only in the high resistance state, when a voltage capable of writing to the cell is applied to the bit line. This is approximately 0.5% of the memory element's operation time, leading to relatively low projected upset rates.

Utilizing device stacking for area efficient hardened SOI flip-flop designs

Abstract: D-flip-flop designs hardened with stacked transistors for a 32-nm SOI CMOS technology show greater than three orders of magnitude decrease in soft error cross-section, up to a heavy-ion tested tilt angle of 55°, and greater than one order of magnitude decrease in cross-section for a heavy-ion tested tilt angle of 75° with less than 50% area penalty compared to unhardened D-flip-flop designs.

TID and Displacement Damage Resilience of 1T1R ${\rm HfO}_2/{\rm Hf}$ Resistive Memories

Abstract: RRAM memory cells demonstrate resilience to ionizing dose and displacement damage, despite the presence of a nonhardened access transistor. Degradation in RRAM performance was not observed until large displacement damage doses and complete functionality was regained by cycling. A significant reduction in both the high and low resistance memory states and a complete collapse of the resistive window was observed for large proton fluences in RRAMs tested. Degradation in resistance states is associated with the generation of additional vacancies, which leads to (an) additional filament(s) in parallel to the existing conductive filament. Additional vacancies from displacement damage in the oxide of the resistive element do not permanently degrade device operation. The low resistance state is recovered to the pre-irradiation resistance through cycling at nominal high-speed switching conditions. Recovery of the resistive window to pre-irradiation values is obtained by applying longer write pulses which migrate remnants of radiation-induced filaments.

Application of the TIARA Radiation Transport Tool to Single Event Effects Simulation

Abstract: Recently (IEEE Trans. Nucl. Sci., Vol. 60, No. 3, pp. 1876-1911, 2013), Reed published an anthology of contributions from different research groups, each developing and/or applying Monte Carlo-based radiation transport tools to simulate a variety of effects that result from energy transferred to a semiconductor material by a single particle event. The Tool suIte for rAdiation Reliability Assessment (TIARA) simulation platform and its development by STMicroelectronics and Aix-Marseille University is described in this paper as a complement to this anthology.

Single-Event Transient and Total Dose Response of Precision Voltage Reference Circuits Designed in a 90-nm SiGe BiCMOS Technology

Abstract: This paper presents an investigation of the impact of single-event transients (SETs) and total ionization dose (TID) on precision voltage reference circuits designed in a fourth-generation, 90-nm SiGe BiCMOS technology. A first-order uncompensated bandgap reference (BGR) circuit is used to benchmark the SET and TID responses of these voltage reference circuits (VRCs). Based on the first-order BGR radiation response, new circuit-level radiation-hardening-by-design (RHBD) techniques are proposed. An RHBD technique using inverse-mode (IM) transistors is demonstrated in a BGR circuit. In addition, a PIN diode VRC is presented as a potential SET and TID tolerant, circuit-level RHBD alternative.

Heavy-Ion and Laser Induced Charge Collection in SiGe Channel $p{\rm MOSFETs}$

Abstract: Heavy-ion and two-photon-absorption (TPA) experiments have been performed on ultra-thin implant-free quantum well SiGe channel pMOSFETs. Both the single-event-transient pulse magnitude and polarity can depend strongly on the location of the strike along the device channel. The polarity inversion occurs primarily because very limited transient charge collection occurs below the quantum well, as confirmed by two-dimensional TCAD simulation.

Single-Event Transient Response of InGaAs MOSFETs

Abstract: The single-event-transient response of InGaAs MOSFETs exposed to heavy-ion and laser irradiations is investigated. The large barrier between the gate oxide and semiconductor regions effectively suppresses the gate transients compared with other types of III-V FETs. After the initial radiation-induced pulse, electrons and holes flood into the channel region at short time. The electrons are collected efficiently at the drain. The slower moving holes accumulate in the channel and source access region and modulate the source-channel barrier, which provides a pathway for transient source-to-drain current lasting for a few nanoseconds. The peak drain transient current reaches its maximum when the gate bias is near threshold and decreases considerably toward inversion and slightly toward depletion and accumulation. Two-dimensional TCAD simulations are used to understand the charge collection mechanisms.

Bias dependence of muon-induced single event upsets in 28 nm static random access memories

Abstract: Experiments performed at TRIUMF and the Rutherford Appleton ISIS facility demonstrate the bias dependence of muon-induced single event upsets in delidded 28 nm static random access memories. Increased probability for upset is observed for memories operating at reduced voltages. Fully packaged parts are shown to be suitable to screen for low-energy muon sensitivity.

Dynamic Modeling of Radiation-Induced State Changes in ${\hbox {HfO}_2}/\hbox {Hf}$ 1T1R RRAM

Abstract: Single and multiple-event upsets in ${\hbox {HfO}_2}/\hbox {Hf}$ one transistor, one resistor (1T1R) resistive random access memory (RRAM) structures are modeled dynamically using 3-D technology computer-aided design (TCAD) simulations. A dynamic single-event compact model is presented that allows direct correlation of the ion-generated voltage transient across the RRAM and the change in RRAM resistance. Experiments and modeling demonstrate an exponential relationship between the susceptibility of the RRAM and the applied voltage. Two implementations of the model are also presented including hardening voltage-susceptible resistive memory technologies and the impact of highly scaled access transistors.

TID and Displacement Damage Resilience of 1T1R

Abstract: RRAM memory cells demonstrate resilience to ion- izing dose and displacement damage, despite the presence of a non- hardened access transistor. Degradation in RRAM performance was not observed until large displacement damage doses and com- plete functionality was regained by cycling. A significant reduction in both the high and low resistance memory states and a complete collapse of the resistive window was observed for large proton flu- ences in RRAMs tested. Degradation in resistance states is asso- ciated with the generation of additional vacancies, which leads to (an)additionalfilament(s)inparalleltotheexistingconductivefila- ment.Additionalvacanciesfromdisplacementdamagein theoxide of the resistive element do not permanently degrade device oper- ation. The low resistance state is recovered to the pre-irradiation resistance through cycling at nominal high-speed switching condi- tions. Recovery of the resistive window to pre-irradiation values is obtained by applying longer write pulses which migrate remnants of radiation-induced filaments.

Validation of the Variable Depth Bragg Peak Method for Single-Event Latchup Testing Using Ion Beam Characterization

Abstract: The Variable Depth Bragg Peak method has been investigated for single event latchup testing by comparing latchup cross sections for heavy ions at low and high energies and by pulse height analysis. Results show that, unlike for an SOI device previously tested, where the charge collection depth is very small (70 nm), the comparison is not straightforward for latchup because of the large charge collection volumes involved. The variation in LET with depth for lower-energy ions greatly affects the comparison, but, if a charge collection depth of 50 μm is assumed and the LET is averaged over that distance, the comparison improves significantly.

Total-Ionizing-Dose Induced Timing Window Violations in CMOS Microcontrollers

Abstract: The total-ionizing-dose robustness of low power microcontrollers is investigated. Experiments reveal that with increasing total ionizing dose (TID), the "Timing Window Vio- lations,"i.e., inability of the instruction set to execute within the clock-cycle(s) lead to failures in microcontroller operations. Clock frequency and supply voltage of the microcontroller are varied to determine the maximum clock frequency at which the micro- controller can execute software subroutines without failure. Low power microcontrollers from two different manufacturers were tested. The maximum clock frequency decreases with increasing TID for both parts. A model for the degradation based on analysis of circuit level timing models is presented. The microcontroller robustness implications for system designers and ASIC designers are discussed. TID has been shown to impact propagation delays in indi- vidual transistors (4), the timing characteristics of integrated circuits (5), memory access times (6), and propagation delays in CMOS flash-based FPGAs (7). In this work, timing window violations are experimentally demonstrated to be the primary source of failure in response to TID for a class of low power microcontrollers, and a model for the degradation and hard- ening implications are presented. The conclusion that timing window violations are the primary source of failure is supported by a measurement technique that allows insight into the in- ternal degradation of the device during the radiation exposure. The technique is necessary when information regarding indi- vidualtransistordegradation,themicrocontrollertechnology,or the fabrication process is not available, such as incorporating a COTS mechatronic subassembly including an integrated mi- crocontroller. Timing window violations are identified by per- forming a series of software tests on the microcontroller at var- ious frequencies and supply voltages. The technique to deter- mine the maximum and minimum frequencies and voltages for the microcontroller is more commonly used in electrical char- acterization (8). Results are presented for a commercially avail- able microcontroller, the Atmel ATMEGA328P (9). Analysis of the experimental results shows that the degradation is con- sistent with the expected degradation of logic gate switching time based on charge build-up in the gate oxide and shallow trench isolation (10). The results are further verified using a subset of the software tests on a Microchip PIC16F677 (11). The clock frequency measurement is nondestructive and can be monitored in a field deployment scenario to evaluate the health of the device, allowing for mission planning as well as life extensionthrough reducingclockoperating frequencyor in- creasing supply voltage.

Multisensor data fusion across time and space

Abstract: Field measurement campaigns typically deploy numerous sensors having different sampling characteristics for spatial, temporal, and spectral domains. Data analysis and exploitation is made more difficult and time consuming as the sample data grids between sensors do not align. This report summarizes our recent effort to demonstrate feasibility of a processing chain capable of “fusing” image data from multiple independent and asynchronous sensors into a form amenable to analysis and exploitation using commercially-available tools. Two important technical issues were addressed in this work: 1) Image spatial registration onto a common pixel grid, 2) Image temporal interpolation onto a common time base. The first step leverages existing image matching and registration algorithms. The second step relies upon a new and innovative use of optical flow algorithms to perform accurate temporal upsampling of slower frame rate imagery. Optical flow field vectors were first derived from high-frame rate, high-resolution imagery, and then finally used as a basis for temporal upsampling of the slower frame rate sensor’s imagery. Optical flow field values are computed using a multi-scale image pyramid, thus allowing for more extreme object motion. This involves preprocessing imagery to varying resolution scales and initializing new vector flow estimates using that from the previous coarser-resolution image. Overall performance of this processing chain is demonstrated using sample data involving complex too motion observed by multiple sensors mounted to the same base. Multiple sensors were included, including a high-speed visible camera, up to a coarser resolution LWIR camera.

Soft errors and NBTI in SiGe pMOS transistors

Abstract: We have investigated single event charge collection and negative-bias instabilities in SiGe pMOSFETs that are of interest for future commercial and space applications. Single-event transient (SET) pulse polarity can depend on the location of the strike along the device channel in ways that differ from SETs in Si-based CMOS devices. The drain bias can significantly affect the total amount of collected charge and peak current values of the SETs in the tested devices. Activation energies for interface-trap buildup during negative bias-temperature stress are lower for SiGe channel pMOSFETs than for Si channel pMOSFETs. Activation energies for oxide-trap charge buildup during negative bias-temperature stress are similar for SiGe pMOSFETs and Si pMOSFETs.