Showing papers by "Cree Inc. published in 2008"

Lighting devices and methods for lighting

Abstract: A lighting device comprises groups of solid state light emitters, a sensor and circuitry. If the emitters are illuminated, the sensor is exposed to combined light from the groups, and senses only a portion of the combined light. The circuitry adjusts current applied to at least one of the emitters based on an intensity of the light sensed. Also, a device comprising emitters, a circuit board and a sensor, at least one of the emitters being positioned on the first circuit board and the sensor being spaced from the circuit board. Also, a lighting device comprising emitters, a sensor, and circuitry which adjusts current applied an emitters based on detection by the first sensor, the circuitry comprising a differential amplifier circuit. Also, a lighting device, comprising light emitters and circuitry which adjusts current applied to only some of the emitters based on ambient temperature. Also, methods of lighting.

Illumination devices using externally interconnected arrays of light emitting devices, and methods of fabricating same

Abstract: A light emitter, comprising light emitting devices mechanically intei connected by a common substrate and an interconnection submount. The light emitting devices are electrically interconnected by the submount to provide an an ay of serially connected subsets of light emitting devices, each subset comprising at least three light emitting devices electrically connected in parallel. Also, a light emitter comprising first light emitting devices mechanically interconnected by a first common substrate, and second light emitting devices mechanically interconnected by a second common substrate, the first light emitting devices being mechanically and electrically connected to the second light emitting devices Also, a light emitter comprising mechanically interconnected light emitting devices and means for mechanically and electrically interconnecting the plurality of light emitting devices to provide an array of serially connected subsets of light emitting devices, each subset comprising at least three light emitting devices electrically connected in parallel. Also, methods of fabricating light emitters.

Solid state linear array modules for general illumination

Abstract: An illumination module includes a longitudinal support member including a base portion and a pair of sidewalls extending from the base portion that together define a channel that extends in a longitudinal direction. A printed circuit board (PCB) on the base portion extends in the longitudinal direction within the channel. A plurality of light emitting diodes (LEDs) are on the PCB in a linear array. A reflective sheet is within and extends across the channel, and includes a plurality of holes that correspond with locations of the LEDs on the PCB, and the LEDs are at least partially within the holes. An optical film extends across the channel above the reflective sheet and defines an optical cavity between the reflective sheet and the optical film. The optical film, the reflective sheet and the sidewalls of the support member are configured to recycle light in the optical cavity by reflecting some light emitted by the LEDs back into the optical cavity and transmitting some light emitted by the LEDs out of the optical cavity.

Phosphor coating systems and methods for light emitting structures and packaged light emitting diodes including phosphor coating

Abstract: Methods are disclosed including applying a layer of binder material onto an LED structure. A luminescent solution including an optical material suspended in a solution is atomized using a flow of pressurized gas, and the atomized luminescent solution is sprayed onto the LED structure including the layer of binder material using the flow of pressurized gas.

Encapsulation for phosphor-converted white light emitting diode

Abstract: An improved light emitting device, especially a phosphor-converted white light device, wherein the light extraction efficiency and the color temperature distribution uniformity are improved by the introduction of both nanoparticles and light scattering particles proximate to the light source. Nanoparticles having a high index of refraction are dispersed throughout a wavelength conversion layer to adjust the index of refraction of the layer for improved light extraction. Light scattering particles may be dispersed in the wavelength conversion layer and/or in a surrounding medium to improve the spatial correlated color temperature uniformity.

Light emitting devices having current reducing structures and methods of forming light emitting devices having current reducing structures

Abstract: A light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. A non-transparent feature, such as a wire bond pad, is on the p-type semiconductor layer or on the n-type semiconductor layer opposite the p-type semiconductor layer, and a reduced conductivity region is in the p-type semiconductor layer or the n-type semiconductor layer and is aligned with the non-transparent feature. The reduced conductivity region may extend from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region and/or from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region.

Solid state lighting devices and methods of manufacturing the same

Abstract: Lighting devices comprising first, second and third strings of solid state lighting devices One aspect further comprises means for supplying first fixed current through the first string, means for supplying second fixed current through the second string, and means for supplying current through the third string In a second aspect, the first and second strings emit light within a specific area on a 1931 CIE Chromaticity Diagram, and the third string emits light of dominant wavelength 600-640 nm A third aspect further comprises a power line and a power supply configured to supply a first and second fixed currents through the first and second strings, respectively, and supply a current to the third string A method of making a lighting device, comprising measuring color output, adjusting current to first, second and/or third strings, and permanently setting currents to the first and second strings

Recent progress in SiC DMOSFETs and JBS diodes at Cree

Abstract: This paper discusses the recent progress in large area silicon carbide (SiC) DMOSFETs and junction barrier Schottky (JBS) diodes 12 kV and 10 kV SiC DMOSFETs have been produced with die areas greater than 064 cm2 SiC JBS diode dies also rated at 12 kV and 10 kV have been produced with die areas exceeding 15 cm2 These results demonstrate that SiC power devices provide a significant leap forward in performance for industrial electronics applications At 12 kV, SiC DMOSFETs offer a reduction of power loss of greater than 50 % with dies less than half the size when compared to silicon (Si) IGBTs The SiC JBS diodes offer significant reductions in reverse recovery losses At 10 kV, there are no Si devices that can compete with SiC on a single device basis Data on 12 kV and 10 kV devices are presented along with future trends

Flip-chip phosphor coating method and devices fabricated utilizing method

Abstract: Methods for fabricating light emitting diode (LED) chips one of which comprises flip-chip mounting a plurality of LEDs on a surface of a submount wafer and forming a coating over said LEDs. The coating comprising a conversion material at least partially covering the LEDs. The coating is planarized to the desired thickness with the coating being continuous and unobstructed on the top surface of the LEDs. The LEDs chips are then singulated from the submount wafer. An LED chip comprising a lateral geometry LED having first and second contacts, with the LED flip-chip mounted to a submount by a conductive bonding material. A phosphor loaded binder coats and at least partially covers the LED. The binder provides a substantially continuous and unobstructed coating over the LED. The phosphor within the coating absorbs and converts the wavelength of at least some of the LED light with the coating planarized to achieve the desired emission color point of the LED chip.

Performance and Stability of Large-Area 4H-SiC 10-kV Junction Barrier Schottky Rectifiers

Abstract: The forward and reverse bias dc characteristics, the long-term stability under forward and reverse bias, and the reverse recovery performance of 4H-SiC junction barrier Schottky (JBS) diodes that are capable of blocking in excess of 10 kV with forward conduction of up to 10 A at a forward voltage of less than 3.5 V (at 25degC) are described. The diodes show a positive temperature coefficient of resistance and a stable Schottky barrier height of up to 200degC. The diodes show stable operation under continuous forward current injection at 20 A/cm2 and under continuous reverse bias of 8 kV at 125degC. When switched from a 10-A forward current to a blocking voltage of 3 kV at a current rate-of-fall of 30 A/mus, the reverse recovery time and the reverse recovery charge are nearly constant at 300 ns and 425 nC, respectively, over the entire temperature range of 25degC-175degC.

LED array and method for fabricating same

Abstract: A light emitting device or array comprising a submount having a top surface, a bottom surface and a plurality of edges, with input and output terminals disposed on the top surface. A plurality of attach pads and traces are also disposed on the top surface and electrically connected between the input and output terminals. A plurality of LEDs are also included, each of which is mounted to one of the attach pads. The attach pads cover more of the top surface than the LEDs and spread heat from the LEDs to the top surface of the submount. A plurality of lenses are also included each of which is molded over a respective one of the attach pads and covers the LED mounted to the particular attach pad. The arrays are shaped and arranged so that they can be easily attached to similar arrays in a tiling fashion, with the desired number of arrays included to meet the desired lighting requirements. Methods for fabricating the arrays from a single submount or submounts panel are also disclosed.

Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides

Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

Wafer level phosphor coating technique for warm light emitting diodes

Abstract: Methods for wafer level fabricating of light emitting diode (LED) chips are disclosed with one embodiment of a method according to the present invention comprising providing a plurality of LEDs and then coating of the LEDs with a layer of first conversion material so that at least some light from the LEDs passes through the first conversion material The light is converted to different wavelengths of light having a first conversion material emission spectrum The LEDs are then coated with a layer of second conversion material arranged on the first layer of conversion The second conversion material has a wavelength excitation spectrum, and at least some light from the LEDs passes through the second conversion material and is converted The first conversion material emission spectrum does not substantially overlap with the second conversion material excitation spectrum Methods according to the present invention can also be used in wafer level fabrication of LED chips and LED packages with pedestals for electrically contacting the LEDs through the conversion coatings

Light emitting devices with high efficiency phospor structures

Abstract: A light emitting device includes a light emitting die (24) configured to emit light having a first dominant wavelength, and an index matched wavelength conversion structure (10, 60) configured to receive light emitted by the light emitting die (24). The index matched wavelength conversion structure (10, 60) includes wavelength converting particles (14) having a first index of refraction embedded in a matrix material (12). The matrix material (12) has a second index of refraction that may be substantially matched to the first index of refraction. The light emitting device may include a graded index layer (50) having an index of refraction that is continuously graded from a first index of refraction in a first region of the graded index layer (50) near the light emitting die (24) to a second index of refraction in the graded index layer (50) away from the light emitting die (24).

A 13 kV 4H-SiC n-Channel IGBT with Low Rdiff,on and Fast Switching

Abstract: For the first time, high power 4H-SiC n-IGBTs have been demonstrated with 13 kV blocking and a low Rdiff,on of 22 mWcm2 which surpasses the 4H-SiC material limit for unipolar devices. Normally-off operation and >10 kV blocking is maintained up to 200oC base plate temperature. The on-state resistance has a slight positive temperature coefficient which makes the n-IGBT attractive for parallel configurations. MOS characterization reveals a low net positive fixed charge density in the oxide and a low interface trap density near the conduction band which produces a 3 V threshold and a peak channel mobility of 18 cm2/Vs in the lateral MOSFET test structure. Finally, encouraging device yields of 64% in the on-state and 27% in the blocking indicate that the 4H-SiC n-IGBT may eventually become a viable power device technology.

Increase in oxide hole trap density associated with nitrogen incorporation at the SiO2/SiC interface

Abstract: Nitrogen incorporation at the SiO2/SiC interface via high temperature nitric oxide annealing leads to the passivation of electrically active interface defects, yielding improved inversion mobility in the semiconductor. However, we find that such nitrided oxides can possess a larger density of hole traps than as-grown oxides, which is detrimental to the reliability of devices (e.g., can lead to large threshold voltage instabilities and to accelerated failure). Three different charge injection techniques are used to characterize this phenomenon in metal–oxide–semiconductor structures: x-ray irradiation, internal photoemission and Fowler–Nordheim tunneling. Some nitrogen-based atomic configurations that could act as hole traps in nitrided SiO2 are discussed based on first-principles density functional calculations.

LED backlight system for LCD displays

Abstract: A LCD system including multiple light sources optically coupled through different light entry regions to at least one waveguide element positioned to backlight a LCD panel. A LCD system including multiple light sources coupled to light entry regions of two or more waveguides comprising a waveguide system positioned to backlight a LCD panel. Waveguides of various configurations and promoting even lighting of associated LCD panels are provided. Resulting LCD systems enable uniformly lit panels having diagonal measurements in excess of 12 to 14 inches, but the invention is not limited to panels of any particular size.

Design and Characterization of High-Voltage 4H-SiC p-IGBTs

Abstract: High-voltage p-channel 4H-SiC insulated gate bipolar transistors (IGBTs) have been fabricated and characterized. The devices have a forward voltage drop of 7.2 V at 100 A/cm2 and a -16 V gate bias at 25degC, corresponding to a specific on-resistance of 72 mOmega ldr cm2 and a differential on-resistance of 26 mmOmega ldr cm2. Hole mobility of 12 cm2/V ldr s in the inversion channel with a threshold voltage of -6 V was achieved by optimizing the n+ well doping profile and gate oxidation process. A novel current enhancement layer was adopted to reduce the JFET resistance and enhance conductivity modulation by improving hole current spreading and suppressing the electron current conduction through the top n-p-n transistor. Inductive switching results have shown that the p-IGBT exhibited a turn-off time of ~1 mus and a turn-off energy loss of 12 m J at 4-kV dc-link voltage and 6-A load current at 25degC. The turn-off trajectory from the measured inductive load switching waveforms and numerical simulations shows that the p-IGBT had a near-square reverse bias safe operating area. Numerical simulations have been conducted to achieve an improved tradeoff between forward voltage drop and switching off energy by investigating the effects of drift layer lifetime and p-buffer layer parameters. The advantages of SiC p-IGBTs, such as the potential of very low ON-state resistance, slightly positive temperature coefficient, high switching speed, small switching losses, and large safe operating area, make them suitable and attractive for high-power high-frequency applications.

Semiconductor light emitting device packages and methods

Abstract: A submount for a light emitting device package includes a rectangular substrate. A first bond pad and a second bond pad are on a first surface of the substrate. The first bond pad includes a die attach region offset toward a first end of the substrate and configured to receive a light emitting diode thereon. The second bond pad includes a bonding region between the first bond pad and the second end of the substrate and a second bond pad extension that extends from the bonding region along a side of the substrate toward a corner of the substrate at the first end of the substrate. First and second solder pads are a the second surface of the substrate. The first solder pad is adjacent the first end of the substrate and contacts the second bond pad. The second solder pad is adjacent the second end of the substrate and contacts the first bond pad. Related LED packages and methods of forming LED packages are disclosed.

Low index spacer layer in LED devices

Abstract: A light emitting diode (LED) device having a low index of refraction spacer layer separating the LED chip and a functional layer. The LED chip has a textured light emission surface to increase light extraction from the chip. The spacer layer has an index of refraction that is lower than both the LED chip and the functional layer. Most of the light generated in the LED chip passes easily into the spacer layer due to the textured surface of the chip. At the interface of the spacer layer and the functional layer the light sees a step-up in index of refraction which facilitates transmission. A portion of the light that has passed into the functional layer will be reflected or scattered back toward the spacer layer where some of it will experience total internal reflection. Total internal reflection at this interface may increase extraction efficiency by reducing the amount of light that re-enters the spacer layer and, ultimately, the LED chip where it may be absorbed. The spacer layer also provides a thermal buffer between the LED chip and the functional layer. Thus, the functional layer, which may be a wavelength conversion layer comprising phosphors, for example, is insulated from direct thermal transfer from the LED chip. The spacer layer can also function as a passivation layer.

Ultra-low resistivity Al+ implanted 4H–SiC obtained by microwave annealing and a protective graphite cap

Abstract: In this work, we have employed a graphite cap for rapid microwave annealing of aluminum implanted 4H–SiC, in the temperature range of 1750–1900 °C, for 30 s durations. The graphite cap prevailed even for 1900 °C/30 s microwave annealing yielding a low surface roughness of 2.4 nm. Rutherford backscattering-channeling spectra indicated that 1900 °C microwave annealing is much more effective than 1800 °C/5 min conventional furnace annealing in not only alleviating the implantation-induced lattice damage but also in removing some of the defects introduced during growth of the 4H–SiC epi-layer used for the Al + implantation. Van der Pauw–Hall measurements indicated an extremely low sheet resistance of 2.8 kΩ/□ for the 1900 °C/30 s annealing, which is about 5 times smaller than the sheet resistance measured on the 1800 °C/5 min conventional furnace annealed material.

Methods of fabricating silicon carbide power devices by at least partially removing an n-type silicon carbide substrate, and silicon carbide power devices so fabricated

Abstract: A silicon carbide power device is fabricated by forming a p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate, and forming a silicon carbide power device structure on the p-type silicon carbide epitaxial layer. The n-type silicon carbide substrate is at least partially removed, so as to expose the p-type silicon carbide epitaxial layer. An ohmic contact is formed on at least some of the p-type silicon carbide epitaxial layer that is exposed. By at least partially removing the n-type silicon carbide substrate and forming an ohmic contact on the p-type silicon carbide epitaxial layer, the disadvantages of using a p-type substrate may be reduced or eliminated. Related structures are also described.

Ultrashallow defect states at SiO2∕4H–SiC interfaces

Abstract: Interface state density (Dit) at SiO2∕4H–SiC interfaces are reported for states lying energetically within ∼0.05–0.2eV of the conduction band edge (EC) of 4H–SiC using capacitance-voltage characterization as a function of temperature. Comparison of as-grown dry oxidized and nitrided interfaces confirms the significant reduction of Dit associated with nitridation. In the as-oxidized case (no nitridation), the Dit in the energy range ∼0.05–0.2eV below EC is found to consist of a broad Dit peak at about ∼0.1eV below EC with an energy width of about ∼0.2eV and a peak magnitude of ∼2×1013cm−2eV−1 superimposed on an exponentially decaying background distribution. Interfacial nitridation completely eliminates the broad peak but does not strongly affect the background.

High Temperature Ion Implantation of Nitride Based HEMTS

Abstract: A method is disclosed for forming a high electron mobility transistor. The method includes the steps of implanting a Group III nitride layer at a defined position with ions that when implanted produce an improved ohmic contact between the layer and contact metals, with the implantation being carried out at a temperature higher than room temperature and hot enough to reduce the amount of damage done to the Group III nitride layer, but below a temperature at which surface problems causing leakage at the gate or epitaxial layer dissociation would occur. An ohmic contact selected from the group consisting of titanium, aluminum, nickel and alloys thereof is added to the implanted defined position on the Group III nitride layer.

Some Critical Materials and Processing Issues in SiC Power Devices

Abstract: There has been a rapid improvement in SiC materials and power devices during the last few years. However, the materials community has overlooked some critical issues, which may threaten the emergence of SiC power devices in the coming years. Some of these pressing materials and processing issues will be presented in this paper. The first issue deals with the possibility of process-induced bulk traps in SiC immediately under the SiC/SiO2 interface, which may be involved in the reduction of effective inversion layer electron mobility in SiC metal–oxide–semiconductor field-effect transistor (MOSFETs). The second issue addresses the effect of recombination-induced stacking faults (SFs) in majority carrier devices such as MOSFETs, Schottky diodes, and junction field-effect transistors (JFETs). In the past it was assumed that the SFs only affect the bipolar devices such as PiN diodes and thyristors. However, most majority carrier devices have built-in p–n junction diodes, which can become forward biased during operation in a circuit. Thus, all high-voltage SiC devices are susceptible to this phenomenon.

Development of Large Area (up to 1.5 cm2) 4H-SiC 10 kV Junction Barrier Schottky Rectifiers

Abstract: DC characteristics and reverse recovery performance of 4H-SiC Junction Barrier Schottky (JBS) diodes capable of blocking in excess of 10 kV with forward conduction of 20 A at a forward voltage of less than 4 V are described. Performance comparisons are made to a similarly rated 10 kV 4H-SiC PiN diode. The JBS diodes show a significant improvement in reverse recovery stored charge as compared to PiN diodes, showing half of the stored charge at 25°C and a quarter of the stored charge at 125°C when switched to 3 kV blocking. These large area JBS diodes were also employed to demonstrate the tremendous advances that have recently been made in 4H-SiC substrate quality.

Ohmic contacts to nitrogen polarity GaN

Abstract: Contacting materials and methods for forming ohmic contact to the N-face polarity surfaces of Group-III nitride based semiconductor materials, and devices fabricated using the methods One embodiment of a light emitting diode (LED) a Group-III nitride active epitaxial region between two Group-III nitride oppositely doped epitaxial layers The oppositely doped layers have alternating face polarities from the Group III and nitrogen (N) materials, and at least one of the oppositely doped layers has an exposed surface with an N-face polarity A first contact layer is included on and forms an ohmic contact with the exposed N-face polarity surface In one embodiment, the first contact layer comprises indium nitride

LEDs USING SINGLE CRYSTALLINE PHOSPHOR AND METHODS OF FABRICATING SAME

Abstract: Methods for fabricating LED chips from a wafer and devices fabricated using the methods with one method comprising depositing LED epitaxial layers on an LED growth wafer to form a plurality of LEDs on the growth wafer. A single crystalline phosphor is bonded over at least some the plurality of LEDs so that at least some light from the covered LEDs passes through the single crystalline phosphor and is converted. The LED chips can then be singulated from the wafer to provide LED chips each having a portion of said single crystalline phosphor to convert LED light.

Light Emitting Diodes with Light Filters

Abstract: LED chips including an LED layer or layers capable of emitting light of a first wavelength, a light conversion layer on the LED capable of converting at least a portion of the light of a first wavelength to light of a second wavelength, and a filter layer therebetween that is transmissive to light of a first wavelength and reflective to light of a second wavelength. The filter layer may prevent at least some of the light of a second wavelength from entering the LED layer or layers, where it may be subject to various optical losses, such as internal reflection and absorption. LED chips may also include multiple filter and light conversion layers. Methods of fabrication are also disclosed.

Power semiconductor devices with mesa structures and buffer layers including mesa steps

Abstract: A bipolar junction transistor includes a collector having a first conductivity type, a drift layer having the first conductivity type on the collector, a base layer on the drift layer and having a second conductivity type opposite the first conductivity type, a lightly doped buffer layer having the first conductivity type on the base layer and forming a p-n junction with the base layer, and an emitter mesa having the first conductivity type on the buffer layer and having a sidewall. The buffer layer includes a mesa step adjacent to and spaced laterally apart from the sidewall of the emitter mesa, and a first thickness of the buffer layer beneath the emitter mesa is greater than a second thickness of the buffer layer outside the mesa step.