Yeshwantrao Chavan College of Engineering

About: Yeshwantrao Chavan College of Engineering is a based out in . It is known for research contribution in the topics: Inverter & Microstrip antenna. The organization has 632 authors who have published 586 publications receiving 4037 citations.

Design of low voltage flip-flop based on complementary pass-transistor adiabatic logic circuit

Abstract: This paper presents To design a low voltage flip-flops based on CPAL circuit. The Complementary Pass-Transistor Adiabatic Logic is used to release flip-flops circuits with DTCMOS (Dual Threshold CMOS) techniques. All circuits are simulated using 180nm Tanner model technology by varying supply voltages. Based on the simulation results, the flip-flop working along with the power-gating technique is realized by CPAL which work on low voltage medium which help to increase speed of the execution. We use Ac power supply which work as low power characteristics of complementary pass-transistor logic (CPL) circuit. Power-clock scheme is more suitable for the design of flip-flops using two phase sequential circuits because it helps to decrease more transistors. The Adiabatic flip-flop has large energy saving over wide range of frequencies.

A Brief Review on Reversible Data Hiding in Encrypted Image

Abstract: To provide the secure communication, data encryption is the best way. In this paper, very easy, quick and authenticate encryption scheme is proposed . The Data hiding in encrypted image plays a vital role for authentication purpose. In A-S algorithm using symmetric stream cipher data hiding is performed. Encryption key and data hiding key can be uses by the user. Image encryption is performed with the help of A-S algorithm. After the encryption is performed, in encrypted image, data hiding key helps to hide the data. Containing auxiliary data with an encrypted image, auxiliary data can extract if receiver has data hiding key, the received data can decrypt to get the image identical to the original image if receiver has encryption key, auxillary data can extract and recovered the original data without any distortion if receiver has both keys. With this techniques the retrived image achives a good PSNR value.

Optimizing weigh feeder performance using modeling and simulation

Abstract: A weigh feeder system is a small conveyor integrated with a belt weigh bridge and speed sensor and driven by a variable speed Motor. These are widely used in Mineral/Ore and chemical industry where a measured rate of solid raw material is fed to Reactors and furnaces. In order to accurately control solid flow rate, the speed of motor/ belt is varied to compensate for the variation of quantity of solid being fed on the belt. Traditionally, such electro-mechanical systems are modeled as IInd order system which ignores the non-linearity due to dead zone and frictions in the geared motor. However, as the weigh feeder is slow speed machine, the non-linearity exhibited by the machine has a bearing on fine speed control therefore the accuracy especially at low speeds. Any inaccuracy in solid feed rate affects quality and efficiency of downstream process. In order to study the effects of friction, this paper develops the model of the electro-mechanical system of an industrial weigh feeder system and studies the dynamic response of the system using MATALB SIMULINK. The results of the simulation are used to propose an innovative calculation based self-tuning discreet time PI controller to improve the control performance of the machine.

Design of constant delay logic style for high speed adder

Abstract: Low power microelectronics has become more intense and low power VLSI systems having emerged as greatly in demand. For increasing number of portable applications require small area low power high throughput. High speed high throughput, small silicon area and at the same time low power consumption is the motivation behind this. This paper presents an effective approach of constant delay (CD) logic style targeting at high-speed applications. Characteristic of this CD logic style without concern of the logic type makes it suitable in implementing complicated logic expressions such as addition. A “timing window” technique is also proposed to reduce the amount of excessive power dissipation in the CD approach. The concept is validated through the simulation of 32-bit Carry look ahead adder with Constant delay logic style using Tanner EDA v13.0.

Wavelet-based technique for texture classification

Abstract: This paper presents a technique for texture feature extraction and classification using wavelet transform. A image is decomposed into no. of sub-bands after applying Wavelet transform to it. A three level decomposition is carried out. A number of sub-bands are generated after wavelet decomposition. An energy signature is computed for each sub-band of these wavelet coefficients. A k-nearest neighbor's classifier is then employed to classify texture patterns. To test and evaluate the method, several sets of textures along with different wavelet bases are employed. Experimental results show superiority of the proposed method.