Yeshwantrao Chavan College of Engineering

About: Yeshwantrao Chavan College of Engineering is a based out in . It is known for research contribution in the topics: Inverter & Microstrip antenna. The organization has 632 authors who have published 586 publications receiving 4037 citations.

Design of iterative data flow graph using hierarchical folding

Abstract: Folding transformation systematically determines the control circuits in digital signal processing architectures which are described by data flow graph (DFG). For a specified folding set and technology constraints it gives architecture represented by hardware DFG. In iterative DFG which can be represented as cascade of similar substructures, rather than applying folding transformation on whole DFG, hierarchical folding folds one substructure and then folding is completed after appropriately changing the number of delays and switch instances in the resulted structure. This paper introduces two ways of applying hierarchical folding namely hierarchical interleaved folding and hierarchical contiguous folding. Its advantages signifies reduction in area required for implementation and run time. From experimental results it is proved that the area requirement and execution time is reduced for two stage sixth order infinite impulse response filter by hierarchical folding over conventional one.

VLSI design of 64bit × 64bit high performance multiplier with redundant binary encoding

Abstract: For multiplier dominated applications such as digital signal processing, wireless communications, and computer applications, high speed multiplier designs has always been a primary requisite. In this paper a high performance 64×64 bit redundant binary (RB) multiplier have been designed by using recently proposed redundant binary encoding approach to eliminate the error correcting word and a delay efficient parallel prefix Ling adder for final redundant binary to normal binary (RB-NB) conversion. Since redundant binary (RB) representation allows carry-free addition and adaptability, it has been used in 64×64 bit high-performance RB multiplier design for summation of partial product terms. The design of multiplier also reduces redundant partial product accumulation stage when eliminating the error correcting word which improves the complexity and the critical path delay. The performance of RB multiplier design compared with conventional RB modified booth encoding multiplier (CRBMBE). The comparison is based on synthesis result obtained by synthesizing both multiplier architectures targeting a Xilinx FPGA in terms of area and delay analysis.

LoRa Technology Based Low Cost Water Meter Reading System

Abstract: Mechanical water meter with AMR capabilities is currently widely used in many cities of India. This legacy system is inaccurate and inefficient as manual data readings is involved in it thus making it labor intensive. In this paper we present a low cost, accurate and reliable solution for reading water meter by building a custom read out device with LoRa transreceiver for communication in the existing system. LoRa RF platform is a two-way wireless IOT based solution that balances M2M (machine to machine) cellular infrastructure and provides a low-cost technique to connect battery operated devices to network infrastructure. To be well-suited with the conventional water meter, this system is mounted over the body of existing meter. A refinement key is based on sensors, microcontroller, LCD display, EEPROM and long range (LoRa) transreceiver. The water meter data is established at the billing system by hand-held device comprising LoRa Transreceiver module. The wished-for system is cost effective and gives automated water meter reading at high accuracy.