Yeshwantrao Chavan College of Engineering

About: Yeshwantrao Chavan College of Engineering is a based out in . It is known for research contribution in the topics: Inverter & Microstrip antenna. The organization has 632 authors who have published 586 publications receiving 4037 citations.

Implementation of PDF crawler using boolean inverted index and n-gram model

Abstract: Today's world are mostly dependent on internet and electronic devices. Most of the users wish to store their information in PDF document, retrieval of such document are most formidable task. To overcome this problem, PDF crawler is implemented. PDF document can be retrieved using keyword and key-phrase present in it. The extraction of keyword is based on Boolean inverted index where as key-phrase is extracted using n-gram algorithm. The pre-processing of PDF document begins with assigning term frequency (TF) to each and every word available in it as well as each document is mapped with unique id called as (docID). After mapping the keyword with term-frequency it extract the keyword which has highest count and store into the database using inverted index with pair of docID and keyword. The key-phrase is extracted by using n-gram. Inverted index makes the pdf crawler faster by storing the documents at one place which contains the same keyword. It helps to reduce storage space as well as it optimized the time required to retrieve the document.

Area-reduced parallel FIR digital filter structures based on Modified Winograd Algorithm

Abstract: This paper shows the implementation of 2-parallel 24 tap Finite Impulse Response Filter using Modified Winograd Algorithm. This technique is efficient in terms of area. This paper also analyses the filter performance using different adders like Carry Select Adder (CSA), Ripple Carry Adder (RCA) and Wallace Multiplier. Symmetric coefficient sub filter blocks are designed using inherent nature of symmetric filter coefficients. In symmetric coefficient sub filter block, the number of multiplier reduced to half. The structure is optimized by minimizing multipliers at the cost of additional adder in pre-processing and post processing blocks. Replacing multipliers with adders is always beneficial. Since silicon area required for multipliers is always less as compared to adders.

Impact of distance metrics on the performance of k-means and fuzzy c-means clustering – an approach to assess student’s performance in e-learning environment

Abstract: Clustering plays a vital role in the various areas of research. In clustering algorithm, distance metrics is key constitute in finding regularities in the data objects. Distance metrics are use as similarity measures. The similarity measures used in clustering are mostly distance based. Distance metrics are not always good enough. Distance metric does not work well when to capture correlations among the data objects. Choosing the right distance metric for a given dataset is a great challenge. In this paper, impact of three different metrics Euclidean, Manhattan and Pearson coefficient correlation on the performance of k-means and fuzzy c-means clustering is presented. In clustering, detection of similarity using distance metrics affects the accuracy of the algorithm. This study helps the researchers to take quick decision about choice of metric for clustering

Implementation of three operand floating point adder

Abstract: In this paper, a three operand floating point adder with reduced delay has been implemented. In this, the internal width which mainly gives the delay has been given compatible with IEEE Std-754. Here for designing three operand floating point adder, Realignment method, which avoid more than one sticky generation, an low cost OR-logic network in the replacement of comparer has been employed, to detect catastrophic cancellation. For implementing three operand floating point adder, Carry save Adder (CSA) is used rather than Ripple Carry adder (RCA) as CSA requires less time to process the input as compared to RCA. To optimize the architecture of complete design, leading zero anticipator (LZA) and compound adder are used. In the proposed design the delay is reduced by 7.79% as compared with the referred three operand adder.

Modified quasi static energy recovery adiabatic logic implementation for low power application

Abstract: This paper presents implementation of flip flops and 3 bit binary up counter using Modified Quasi State Energy Recovery Logic (MQSERL). Two phase power clock supply and its 1800 phase shifted signal is used in MQSERL to minimize switching activities of circuit node. Initially circuits such as INVERTER, NAND, NOR, XOR and 2:1 multiplexer have been designed using MQSERL style and conventional CMOS logic. Comparative analysis has been done by computing power dissipation, propagation delay and Power Delay Product to validate the functionality of proposed MQSERL. Further D flip flop with preset and clear terminal have been designed using three input NAND gate and then 3 bit binary up counter using both the logic styles. All the circuits are simulated using 180nm tanner technology and at operating voltage of 1.8v. Clock frequency for MQSERL is set at 100MHz and input signal at 50 MHz. The MQSERL D flip Flop is 82.21% and 3 bit binary Counter is 94.40% power efficient over conventional CMOS logic.