Journal ArticleDOI
A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13- $\mu $ m CMOS Technology
TLDR
This brief presents a zero-crossing-based pipeline analog-todigital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs.Abstract:
This brief presents a zero-crossing-based pipeline analog-to-digital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs. The ADC uses only simple open-loop amplifiers for residue amplification. Using modified sliding interpolation and subranging techniques, the number of amplifiers is reduced by 60%. A 10-bit 200-MS/s ADC, employing the architecture and other techniques, such as double sampling, digital error correction, and source degeneration, is fabricated in 0.13- $\mu $ m CMOS process and occupies a die area of 0.7 $\mathrm{mm}^{2}$ . The differential and integral nonlinearity of the ADC are less than 0.83/−0.47 and 1.05/−0.7 LSB, respectively. With a 1.5-MHz full-scale input, the ADC achieves 56.5-dB signal-to-noise plus distortion ratio, 71.8-dB spurious free dynamic range, and 9.1 effective number of bits at full sampling rate while dissipating 38 mW from a 1.2-V supply.read more
Citations
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Journal ArticleDOI
A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers
Mohammad H. Naderi,Chulhyun Park,Suraj Prakash,Martin Kinyua,Eric Soenen,Jose Silva-Martinez +5 more
TL;DR: This paper presents a 12-bit 500 MS/s pipelined ADC fabricated in the 40 nm TSMC technology, which aims to reduce the power consumption associated with residue amplifiers and comparator cells and proposes a forecasting technique in the sub-ADC, which reduces the number of active comparators during the sub theADC’s conversion phase.
Journal ArticleDOI
A 13-bit 8-kS/s $\Delta$ – $\Sigma$ Readout IC Using ZCB Integrators With an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR
TL;DR: This paper reports on an energy-efficient readout IC with a high power-supply-rejection ratio (PSRR) with a dual-path bridge measurement aids in upholding PSRR of ROIC against bridge imbalance.
Journal ArticleDOI
An Optimal Design Methodology for Yield-Improved and Low-Power Pipelined ADC
Nahid Mirzaie,Gyung-Su Byun +1 more
TL;DR: The proposed ADC design algorithm incorporates several techniques to enable simultaneous improvement of yield and performance and can achieve a significant reduction of computational burden compared with the modified Monte-Carlo (MC)-based yield improvement methods integrating Latin-hypercube sampling or trimmed-sample MC.
Journal ArticleDOI
Three-Dimensional Pipeline ADC Utilizing TSV/ Design Optimization and Memristor Ratioed Logic
TL;DR: This paper presents a pipeline ADC architecture with a novel 3-D clock distribution network utilizing through-silicon via-induced benefits and implements memristor ratioed logic as the basic elements of digital error correction subblock to further decrease the area, delay, and power consumption.
Journal ArticleDOI
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration
Dadian Zhou,Carlos Briseno-Vidrios,Junning Jiang,Chulhyun Park,Qiyuan Liu,Eric Soenen,Martin Kinyua,Jose Silva-Martinez +7 more
TL;DR: A pipeline analog-to-digital converter (ADC) with high power efficiency and figure-of-merit (FoM) is implemented in this paper.
References
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Journal ArticleDOI
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter
Thomas Byunghak Cho,Paul R. Gray +1 more
TL;DR: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation.
Proceedings Article
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter
Thomas Byunghak Cho,Paul R. Gray +1 more
TL;DR: In this article, the authors describe a 10 b, 20 µm pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation.
Journal ArticleDOI
A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS
M. Choi,Asad A. Abidi +1 more
TL;DR: In this paper, a 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz using array averaging and a wideband track-and-hold is reported.
Journal ArticleDOI
An 8-bit 150-MHz CMOS A/D converter
Yun-Ti Wang,Behzad Razavi +1 more
TL;DR: In this paper, an 8-bit 5-stage pipelined and interleaved analog-to-digital converter that performs analog processing only by means of open-loop circuits such as differential pairs and source followers is described.
Proceedings ArticleDOI
A 6 b 1.3 GSample/s A/D converter in 0.35 μm CMOS
M. Choi,A.A. Abidi +1 more
TL;DR: A 6-b Nyquist A/D converter that converts at 1.3 GHz is reported, using array averaging and a wideband track-and-hold to achieve better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s.