Journal ArticleDOI
A no-snapback LDMOSFET with automotive ESD endurance
TLDR
In this paper, a no-snapback lateral double-diffused MOSFET (LDMOSFet) was proposed for automotive applications under the condition of 15 kV, 150 pF, and 150 /spl Omega/, representing one order of magnitude higher ESD voltage than conventional LDMOS.Abstract:
This paper presents a no-snapback lateral double-diffused MOSFET (LDMOSFET), which endures the electrostatic discharge (ESD) requirement for automotive applications under the condition of 15 kV, 150 pF, and 150 /spl Omega/, representing one order of magnitude higher ESD voltage than conventional LDMOS. First, the mixed (circuit and device) mode simulations analyze the typical ESD failure dynamics of the conventional LDMOSFET, correlating the circuit level transient responses and the device level snapback characteristics (i.e., the negative breakdown voltage-current (V-I) characteristics). Then, the mechanism of the snapback is clarified from the aspect of the feedback link between the turn-on of the parasitic bipolar junction transistor (BJT) and the breakdown of the drain n-n/sup +/ diode. Finally, a no-snapback LDMOSFET is experimentally demonstrated that attains the objective ESD endurance.read more
Citations
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Journal ArticleDOI
Moving current filaments in integrated DMOS transistors under short-duration current stress
Marie Denison,M. Blaho,P. Rodin,V. Dubec,Dionyz Pogany,D. Silber,Erich Gornik,Matthias Stecher +7 more
TL;DR: In this article, the authors studied the influence of termination layout of the source field on the hot-spot dynamics and discussed conditions for filament motion under non-destructive snap-back conditions, which help homogenize the time averaged current density distribution and enhance the device robustness against electrostatic discharges.
Proceedings Article
Current filament movement and silicon melting in an ESD-robust DENMOS transistor
TL;DR: In this article, the authors analyzed and simulated the HBM and TLP results for an 80 V DENMOS transistor and found that the current initially crowd into a small filament, which moves to cooler regions during the extent of the pulse.
Journal ArticleDOI
Thermal Accumulation Effects on the Transient Temperature Responses in LDMOSFETs Under the Impact of a Periodic Electromagnetic Pulse
TL;DR: In this article, thermal accumulation effects in an LDMOSFET under the impact of a periodic electromagnetic pulse (EMP) were investigated using time-domain finite element method combined with the preconditioned conjugated gradient technique.
Proceedings ArticleDOI
Novel Robust High Voltage ESD Clamps for LDMOS Protection
TL;DR: In this paper, robust high voltage LDMOS ESD clamps with embedded SCR's have been TLP tested and implemented in products showing these approaches to be especially useful in overcoming the inherent ESD weakness of low voltage devices.
Proceedings ArticleDOI
Snapback Breakdown Dynamics and ESD Susceptibility of LDMOS
TL;DR: In this article, two different failure modes are observed for a given type of LDMOS, which are dependent upon the effective gate width and geometry of the transistors, and a description and explanation of the different failure mechanisms on the devices with different geometry is provided.
References
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TL;DR: In this article, a dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported and the design issues for optimum output ESD protection are also discussed.
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Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations
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