Journal ArticleDOI
A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits
TLDR
In this article, the authors investigated the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits.Abstract:
The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation circuits of the proposed full adder are designed with hybrid logic styles. To operate at ultra-low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem. As full adders are frequently employed in a tree structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is introduced to evaluate the full adders in a realistic application environment. A systematic and elegant procedure to scale the transistor for minimal power-delay product is proposed. The circuits being studied are optimized for energy efficiency at 0.18-/spl mu/m CMOS process technology. With the proposed simulation environment, it is shown that some survival cells in stand alone operation at low voltage may fail when cascaded in a larger circuit, either due to the lack of drivability or unsatisfactory speed of operation. The proposed hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability. The increase in the transistor count of its complementary CMOS output stage is compensated by its area efficient layout. Therefore, it remains one of the best contenders for designing large tree structured arithmetic circuits with reduced energy consumption while keeping the increase in area to a minimum.read more
Citations
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Journal ArticleDOI
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
TL;DR: The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability and is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously.
Journal ArticleDOI
CMOS Full-Adders for Energy-Efficient Arithmetic Applications
TL;DR: Two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP) outperform its counterparts exhibiting an average PDP advantage.
Journal ArticleDOI
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
TL;DR: In this paper, a hybrid 1-bit full adder design employing both complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic is reported and is found to offer significant improvement in terms of power and speed.
Journal ArticleDOI
Two new low-power Full Adders based on majority-not gates
Keivan Navi,Mohammad Hossein Moaiyeri,Reza Faghih Mirzaee,Omid Hashemipour,Babak Mazloom Nezhad +4 more
TL;DR: Two novel low-power 1-bit Full Adder cells are proposed, based on majority-not gates, which are designed with new methods in each cell, and demonstrate improvement in terms of power consumption and power-delay product (PDP).
Journal ArticleDOI
ULPFA: A New Efficient Design of a Power-Aware Full Adder
TL;DR: Comparisons between adders based on full adders from the prior art and the ULPFA version demonstrate that the development outperforms the static CMOS and the CPL full adder, particularly in terms of power consumption and PDP by at least a factor of two.
References
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Book
Low Power Digital CMOS Design
TL;DR: The Hierarchy of Limits of Power J.D. Stratakos, et al., and Low Power Programmable Computation coauthored with M.B. Srivastava, provide a review of the main approaches to Voltage Scaling Approaches.
Journal ArticleDOI
Low-power logic styles: CMOS versus pass-transistor logic
R. Zimmermann,Wolfgang Fichtner +1 more
TL;DR: This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.
Journal ArticleDOI
Performance analysis of low-power 1-bit CMOS full adder cells
TL;DR: A performance analysis of 1-bit full-adder cell is presented, after the adder cell is anatomized into smaller modules, and several designs of each of them are developed, prototyped, simulated and analyzed.
Proceedings ArticleDOI
Clustered voltage scaling technique for low-power design
Kimiyoshi Usami,Mark Horowitz +1 more
TL;DR: In this paper, the authors present a supply-s.m.s.led supply model for energy-efficient power-saving devices, including solar panels, and rechargeable batteries.
Journal ArticleDOI
A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
TL;DR: The proposed method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known, and it is easy to incorporate this method in silicon compilation or logic synthesis tools.