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Journal ArticleDOI

An accurate gate length extraction method for sub-quarter micron MOSFET's

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TLDR
By comparing measured and simulated gate-to-source/drain capacitances, C/sub gds/, an accurate gate length extraction method is proposed for sub-quarter micron MOSFET's applications.
Abstract
By comparing measured and simulated gate-to-source/drain capacitances, C/sub gds/, an accurate gate length extraction method is proposed for sub-quarter micron MOSFET's applications. We show that by including the 2-D field effect on the fringing capacitance, the polysilicon depletion and the quantum-well effects in the C/sub gds/ simulation, the polysilicon gate length, L/sub poly/, can be accurately determined for device lengths down to the 0.1 /spl mu/m regime. The accuracy of this method approaches that of cross-sectional TEM on the device under test, but without destroying the device. Furthermore, we note that as a result of accurate L/sub poly/ extraction, the source/drain lateral diffusion length, L/sub diff/, and effective channel length, L/sub eff/, can also be determined precisely. The accuracy of L/sub diff/ is confirmed by examining their consistency with experimentally obtained 2-D source/drain profile.

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Citations
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Journal ArticleDOI

Two-dimensional doping profile characterization of MOSFETs by inverse modeling using I-V characteristics in the subthreshold region

TL;DR: In this article, a technique for the characterization of two-dimensional (2D) doping profiles in deep submicron MOSFETs using currentvoltage (I-V) characteristics in the subthreshold region is presented.
Journal ArticleDOI

Accurate Extraction of Effective Channel Length and Source/Drain Series Resistance in Ultrashort-Channel MOSFETs by Iteration Method

TL;DR: In this paper, an improved channel resistance method using an iterative procedure has been proposed, which takes into account the fact that mobility is degraded in shorter channel devices, and more accurate approximations for L eff and R SD are extracted compared to conventional methods.
Journal ArticleDOI

Automatic Extraction Methodology for Accurate Measurements of Effective Channel Length on 65-nm MOSFET Technology and Below

TL;DR: In this paper, the length of MOSFET channels is estimated using gate-to-channel measurements Cgc(Vg) to provide accurate channel length extraction with a maximized reliability.
Proceedings ArticleDOI

Automatic extraction methodology for accurate measurement of effective channel length on 65nm MOSFET technology and below

TL;DR: This paper focuses on a new industrially-compatible technique using gate-to-channel measurements Cgc(Vg) to provide accurate extraction of the channel length using fully-automatic probers to improve the extraction accuracy to within a few nanometers.
References
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Journal ArticleDOI

A new 'shift and ratio' method for MOSFET channel-length extraction

TL;DR: In this paper, a shift-and-ratio method for channel length extraction is presented, where channel mobility can be any function of gate voltage, and high source-drain resistance does not affect extraction results.
Journal ArticleDOI

A simple model for the overlap capacitance of a VLSI MOS device

TL;DR: In this article, a simple approximate analytical expression for the overlap capacitance between gate and source-drain of a VLSI MOS device is derived, taking into account finite polysilicon gate thickness, sourcedrain junction depth and different dielectric constants of silicon and oxide.
Proceedings ArticleDOI

Determination of ultra-thin gate oxide thicknesses for CMOS structures using quantum effects

R. Rios, +1 more
TL;DR: In this article, a new method to determine ultra-thin gate oxide thicknesses of advanced CMOS devices from C-V characteristics is proposed, based on numerical solutions of the Poisson equation including a first order correction for quantum mechanical effects.
Journal ArticleDOI

A new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFET's

TL;DR: In this paper, a new method for determining the channel charge and mobility of a MOS transistor as a function of gate bias from the ac admittance measurements is described, where the peaks of the G/omega versus ω curves are used to deduce gate-channel capacitance and mobility.
Journal ArticleDOI

A capacitance method to determine channel lengths for conventional and LDD MOSFET's

TL;DR: In this article, a simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described, based on the linear relationship between the intrinsic gate capacitance and effective channel length.
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