Journal ArticleDOI
Cathedral-II: A Silicon Compiler for Digital Signal Processing
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TLDR
The Cathedral-II compiler as discussed by the authors is based on a meet in the middle design method that encourages a total separation between system design and reusable silicon design and includes a rule-based synthesis program, a procedural program, and a controller synthesis environment.Abstract:
The article describes the status of work at IMEC on the Cathedral-II silicon compiler. The compiler was developed to synthesize synchronous multiprocessor system chips for digital signal processing. It is a continuation of work on the Cathedral-I operational silicon compiler for bit-serial digital filters. Cathedral-II is based on a ?meet in the middle? design method that encourages a total separation between system design and reusable silicon design. The CAD system includes a rule-based synthesis program, a procedural program, and a controller synthesis environment. Processors are synthesized in terms of modules called from automated reusable module generators. Chip layout is done on a floor planner. An expert subsystem verifies correctness during silicon design and generates functional and timing models for verification at the module and chip levels.read more
Citations
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Force-directed scheduling for the behavioral synthesis of ASICs
P.G. Paulin,J.P. Knight +1 more
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High-Level Synthesis for FPGAs: From Prototyping to Deployment
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The high-level synthesis of digital systems
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A formal approach to the scheduling problem in high level synthesis
TL;DR: An integer linear programming (ILP) model for the scheduling problem in high-level synthesis is presented and a scheduling problem called feasible scheduling, which provides a paradigm for exploring the solution space, is constructed.
Journal ArticleDOI
High-Level Synthesis: Past, Present, and Future
Grant Martin,G. Smith +1 more
TL;DR: The authors offer insights on why earlier attempts to gain industry adoption were not successful, why current HLS tools are finally seeing adoption, and what to expect as HLS evolves toward system-level design.
References
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Proceedings ArticleDOI
Switch-Level Delay Models for Digital MOS VLSI
TL;DR: Three delay models for large digital MOS circuits are presented, ranging from an RC model that typically errs by 25% to a slope-based model whose delay estimates are typically within 10% of SPICE's estimates.
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Automatic Data Path Synthesis
TL;DR: The quality of designs produced by automatic synthesis programs are not yet adequate for production use, but their use as a computer aid permitting designer interaction is becoming a realitv, 1 and promises further.
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The MIMOLA Design System: Tools for the Design of Digital Processors
TL;DR: The MIMOLA design method is a method for the design of digital processors from a very high-level bevavioral specification, supported by a retargetable microcode generator and by an utilization and performance analyzer.
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DIALOG: An Expert Debugging System for MOSVLSI Design
TL;DR: An expert system (DIALOG) is described to check correctness of logic levels and timing composition rules in n- or CMOS VLSI logic to show the feasibility for batch oriented debugging of up to 50,000 transistors in a workstation environment while keeping knowledge programming efficiency of LEXTOC.
Proceedings ArticleDOI
A novel method for pitch extraction from speech and a hardware model applicable to vocoder systems
TL;DR: A new and reliable concept for pitch extraction from speech which has been implemented in hardware and applied in a channel vocoder based on a recently developed model of pitch perception is described.