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Design Of Analog Cmos Integrated Circuits
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Citations
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Journal ArticleDOI
Integrated digital inverters based on two-dimensional anisotropic ReS2 field-effect transistors.
Erfu Liu,Yajun Fu,Yaojia Wang,Yanqing Feng,Huimei Liu,Xiangang Wan,Wei Zhou,Baigeng Wang,Lubin Shao,Ching-Hwa Ho,Ying-Sheng Huang,Zhengyi Cao,Lai-Guo Wang,Aidong Li,Junwen Zeng,Fengqi Song,Xinran Wang,Yi Shi,Hongtao Yuan,Harold Y. Hwang,Harold Y. Hwang,Yi Cui,Yi Cui,Feng Miao,D. Y. Xing +24 more
TL;DR: In this paper, field effect transistors from single and few-layer rhenium disulfide were constructed and observed an anisotropic ratio of three to one along the two principle axes.
Journal ArticleDOI
All-Digital Self-interference Cancellation Technique for Full-duplex Systems
Elsayed Ahmed,Ahmed M. Eltawil +1 more
TL;DR: The overall performance is numerically investigated showing that using the proposed technique, the self-interference signal could be mitigated to ~3 dB higher than the receiver noise floor, which results in up to 76% rate improvement compared to conventional half-duplex systems at 20 dBm transmit power values.
Proceedings ArticleDOI
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case
Donghyuk Lee,Yoongu Kim,Gennady Pekhimenko,Samira Khan,Vivek Seshadri,Kevin K. Chang,Onur Mutlu +6 more
TL;DR: Adaptive-Latency DRAM (AL-DRAM), a mechanism that adoptively reduces the timing parameters for DRAM modules based on the current operating condition, is proposed and shown that dynamically optimizing the DRAM timing parameters can reliably improve system performance.
Journal ArticleDOI
Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain.
Sungsik Lee,Arokia Nathan +1 more
TL;DR: A Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime at low supply voltages and ultralow power is reported, minimizes power consumption by operating near the off-state limit.
Journal ArticleDOI
Printed subthreshold organic transistors operating at high gain and ultralow power.
TL;DR: A high-gain, fully inkjet-printed Schottky barrier organic thin-film transistor amplifier circuit that delivered gain near the theoretical limit at a power below 1 nanowatt and detected electrophysiological signals from the skin with a wearable device is reported.
References
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Proceedings ArticleDOI
Design of Third order Wide Tuning Range Gm-C filter for direct conversion receivers
TL;DR: The design is implemented in the UMC 90 nm CMOS technology and the results show that the power consumption of the designed filter is less than 0.25 mW for maximum cut-off frequency from a 1V supply voltage.
Journal Article
Single Stage and Two Stage OP-AMP Design in 180nm CMOS Technology
Anand Kasundra,Jaydip Ravia,Subhash Technical Campus,Chetan Bhetariya,Himat Chavada,Rajesh Choravada +5 more
TL;DR: In this paper, the authors presented a method for the design of single stage and two stage Op-amp in 180nm CMOS process and simulated diode connected load with two more PMOS to overcome trade-off between the output voltage swing, the voltage gain, and the input CM range.
Dissertation
Enhancement technique for dynamic CMOS current mirror : Application to high-performance current sources in biomedical devices.
TL;DR: Results of the last studies have demonstrated that, thanks to the design strategy and the new active-input current mirror topologies proposed, it is actually possible to outperform the present limit of the speed-power-accuracy trade-off.
Journal Article
A Low Noise OPAMP with Chopper Stabilization for Biomedical Applications
TL;DR: A CMOS (Complementary Metal oxide Semiconductor) design comprising fully differential Operational Amplifier circuit decreases the noise present in the measured input bio potential signals to get low noise levels.
Proceedings ArticleDOI
Input switch configuration for sample and hold circuits in low-voltage operation
TL;DR: In this article, an implementation of Dessouky's bootstrapped switch optimized for 65-nm CMOS technology is presented to attain a high linearity in front-end sample-and-hold (S/H) circuits.