Journal ArticleDOI
Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS
TLDR
In this article, the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on sub-threshold circuit performance for 32 nm bulk CMOS.Abstract:
Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium performance criteria. It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy consumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS. From the study, we conclude that alternative devices like double-gate silicon-on-insulator (DGSOI) are better candidates in terms of performance, robustness and PVT insensitivity as compared to bulk circuits for both static CMOS and pseudo NMOS logic families. We also study the performance and robustness comparisons of bulk CMOS and DGSOI subthreshold basic logic gates with and without parameter variations and we observe 60-70% improvement in power delay product and roughly 50% better tolerance to PVT variations of DGSOI subthreshold logic circuits compared to bulk CMOS subthreshold circuits at the 32 nm node.read more
Citations
More filters
Journal ArticleDOI
Leakage Characterization of 10T SRAM Cell
Aminul Islam,Mohd. Hasan +1 more
TL;DR: In this article, the authors present a technique for designing a low power and variability-aware SRAM cell that achieves low power dissipation due to its series-connected tail transistor and read buffers, which offer a stacking effect.
Journal ArticleDOI
Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell
TL;DR: A Schmitt-trigger-based single-ended 11T SRAM cell is presented, which significantly improves read and write static noise margin (SNM) and consumes low power and achieves the lowest leakage power dissipation among the cells considered for comparison.
Journal ArticleDOI
Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications
Soumitra Pal,Aminul Islam +1 more
TL;DR: Impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended8T (SE8T) SRAM cells.
Journal ArticleDOI
A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell
Aminul Islam,Mohd. Hasan +1 more
TL;DR: Comparison analysis based on Monte Carlo simulation exhibits that the proposed design is capable of mitigating impact of Vt variation to a large extent.
Journal ArticleDOI
9-T SRAM Cell for Reliable Ultralow-Power Applications and Solving Multibit Soft-Error Issue
Soumitra Pal,Aminul Islam +1 more
TL;DR: A double-ended read-decoupled ultralow-power 9-T SRAM cell (LP9T) is proposed, and the proposed cell supports the column bit-interleaving architecture, and its noise tolerance is improved.
References
More filters
Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
Journal ArticleDOI
CMOS analog integrated circuits based on weak inversion operations
Eric A. Vittoz,J. Fellrath +1 more
TL;DR: In this paper, a simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications and verified experimentally for both p-and n-channel test transistors of a Si-gate low-voltage CMOS technology.
Journal ArticleDOI
New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration
TL;DR: In this article, a new generation of predictive technology model (PTM) is developed to predict the characteristics of nanoscale CMOS, including process variations and correlations among model parameters.