Disconnection failure model and analysis of TSV-based 3D ICs

TLDR: In this paper, a gap between a TSV and the corresponding bump is calculated to analyse its effect on the system; the calculated values for 1 μm, 3 μm and 5 μm gap resulted in 14.07 fF, 4.69 fF and 2.82 fF respectively.

Abstract: The trend in semiconductor industry is rapidly shifting from 2-dimension to 3-dimension to satisfy the ever-growing demand on the miniaturization of electronic devices. The introduction of through silicon via (TSV) based 3-dimensional integrated circuit (3D-IC) has significantly advanced the technology to realize high speed system with increased functionality. However, challenges remain in reliability of fabrication and testing methods. The size of transistors and interconnections has shrunk to few tens of nanometers, requiring highly advanced technique in the fabrication process. The precision in existing fabrication process is insufficient to reach the acceptable level of chip yield. Thus, TSV failure detection and analysis is essential for 3D-IC technology. One of the main failures that degrades the chip performance is disconnection failure. Disconnection failure may form in any point along the channel, especially in between the stacked layers. Stacked dies with TSVs as interconnects can be analysed by equivalent circuit model. Each component is represented as lumped components according to its material and physical dimensions. A disconnection along the channel is a gap between two conducting materials, which is modelled as series capacitance. The gap between a TSV and the corresponding bump is calculated to analyse its effect on the system; the calculated values for 1 μm, 3 μm and 5 μm gap resulted in 14.07 fF, 4.69 fF, and 2.82 fF, respectively. The modelled components were inserted and S-parameter plots were extracted for analysis.