Effective Radii of On-Chip Decoupling Capacitors
TLDR
A design methodology for placing on-chip decoupling capacitors is presented and a maximum effective radius is shown to exist for each on- chip decoupled capacitor.Abstract:
Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard cell circuit blocks. The efficacy of on-chip decoupling capacitors depends upon the impedance of the power/ground lines connecting the capacitors to the current loads and power supplies. A design methodology for placing on-chip decoupling capacitors is presented in this paper. A maximum effective radius is shown to exist for each on-chip decoupling capacitor. Beyond this effective distance, a decoupling capacitor is ineffective. Depending upon the parasitic impedance of the power distribution system, the maximum voltage drop seen at the current load is caused either by the first droop (determined by the rise time) or by the second droop (determined by the transition time). Two criteria to estimate the minimum required on-chip decoupling capacitance are developed based on the critical parasitic impedance. In order to provide the required charge drawn by the load, the decoupling capacitor has to be charged before the next switching cycle. For an on-chip decoupling capacitor to be effective, both effective radii criteria should be simultaneously satisfied.read more
Citations
More filters
Journal ArticleDOI
Distributed On-Chip Power Delivery
Selcuk Kose,Eby G. Friedman +1 more
TL;DR: A unified design methodology is proposed to determine the optimal location of the power supplies and decoupling capacitors in high performance integrated circuits.
Journal ArticleDOI
Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance
TL;DR: The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor and an equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ ground noise in the time domain.
Journal ArticleDOI
Deep Reinforcement Learning-Based Optimal Decoupling Capacitor Design Method for Silicon Interposer-Based 2.5-D/3-D ICs
HyunWook Park,Seongguk Kim,Youngwoo Kim,Joungho Kim,Junyong Park,Subin Kim,Kyungjun Cho,Daehwan Lho,Seungtaek Jeong,Shinyoung Park,Gapyeol Park,Boogyo Sim +11 more
TL;DR: A deep reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for silicon interposer-based 2.5-D/3-D integrated circuits (ICs) that provides an optimal decap design that satisfies target impedance with a minimum area.
Journal ArticleDOI
On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits
TL;DR: On-chip resonances in power distribution grids with decoupling capacitors are intuitively explained in this paper, and circuit design implications are provided.
Proceedings ArticleDOI
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits
TL;DR: On-chip resonances in power distribution grids with decoupling capacitors are intuitively explained in this paper, and circuit design implications are provided.
References
More filters
Journal ArticleDOI
Power distribution system design methodology and capacitor selection for modern CMOS technology
TL;DR: In this paper, the impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models.
Book
Power Distribution Networks with On-Chip Decoupling Capacitors
TL;DR: In this article, the authors describe methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing multiple power supplies and decoupling capacitors.
Proceedings ArticleDOI
Design and analysis of power distribution networks in PowerPC/sup TM/ microprocessors
Abhijit Dharchoudhury,Rajendran Panda,David Blaauw,Ravi Vaidyanathan,Bogdan Tutuianu,David Bearden +5 more
TL;DR: A methodology for the design and analysis of power grids in the PowerPC™ microprocessors covering the need for power grid analysis across all stages of the design process is presented.
Journal ArticleDOI
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
TL;DR: Compared to postfloorplan approach, the peak power-supply noise can be reduced by as much as 40% and the decap budget can be reduction by asMuch as 21% by using noise-aware floorplanning methodology.