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Journal ArticleDOI

Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance

TLDR
The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor and an equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ ground noise in the time domain.
Abstract
The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor. The worst case power/ground noise obtained with fast switching characteristics is shown to be significantly inaccurate. An equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. Furthermore, the sensitivity of the ground noise to the decoupling capacitance Cd and parasitic inductance Lg is evaluated as a function of the transition time. Increasing the decoupling capacitance is shown to efficiently reduce the noise for transition times smaller than twice the LC time constant, tr les 2radic(LgCd). Alternatively, reducing the parasitic inductance Lg is shown to be effective for transition times greater than twice the LC time constant, tr ges 2radic(LgCd). The peak noise occurs when the transition time is approximately equal to twice the LC time constant, tr ap 2radic(LgCd) , referred to as the equivalent transition time for resonance.

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Citations
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Journal ArticleDOI

Closed-Form Expressions for the Maximum Transient Noise Voltage Caused by an IC Switching Current on a Power Distribution Network

TL;DR: In this paper, closed-form expressions for transient power distribution network (PDN) noise caused by an IC switching current are derived for a PDN structure comprised of traces with decoupling capacitors.
Journal ArticleDOI

Shielding Methodologies in the Presence of Power/Ground Noise

TL;DR: Design guidelines for shielding in the presence of power/ground (P/G) noise are presented and the effects of technology scaling on P/G noise and shielding efficiency are discussed, and related design tradeoffs are addressed.
Journal ArticleDOI

Power Distribution in TSV-Based 3-D Processor-Memory Stacks

TL;DR: It is demonstrated that the area overhead of a 3-D power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies.
Proceedings ArticleDOI

Distributed power network co-design with on-chip power supplies and decoupling capacitors

TL;DR: The on-chip power supplies and decoupling capacitors within the power network are simultaneously co-designed and placed, and the effect of physical distance on the power supply noise is investigated.
Proceedings Article

Power distribution system design methodology and capacitor selection for modern CMOS technology

TL;DR: The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models.
References
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Journal ArticleDOI

Power distribution system design methodology and capacitor selection for modern CMOS technology

TL;DR: In this paper, the impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models.
Book

Power Distribution Networks with On-Chip Decoupling Capacitors

TL;DR: In this article, the authors describe methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing multiple power supplies and decoupling capacitors.
Journal ArticleDOI

Circuits and techniques for high-resolution measurement of on-chip power supply noise

TL;DR: This paper presents a technique for characterizing the statistical properties and spectrum of power supply noise using only two on-chip low-throughput samplers that utilize a voltage-controlled oscillator to perform high-resolution analog-to-digital conversion with minimal hardware.
Journal ArticleDOI

Interconnect and circuit modeling techniques for full-chip power supply noise analysis

TL;DR: This integrated chip-and-package model provides a complete analysis of the resistive IR drop, inductive delta-I noise, and the on-chip Vdd distribution and allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise.
Journal ArticleDOI

Impact of power-supply noise on timing in high-frequency microprocessors

TL;DR: In this article, the impact of power-supply noise on the performance of high-frequency microprocessors is analyzed. But the authors focus on the average supply voltage during switching.
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