Journal ArticleDOI
Effects of avalanche injection of electrons into silicon dioxide—generation of fast and slow interface states
S. K. Lai,D. R. Young +1 more
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In this article, it is shown that the slow states can be discharged when heated under +5 V or higher biases at 160°C or above, and the fast states are also annealed in the process, and enhanced by a positive bias.Abstract:
In the process of avalanche injection of electrons into silicon dioxide, besides electron trapping in the bulk of the oxide, there are slow and fast interface states generated. The slow states are donors and positively charged when empty. Together with positive charge in the interface states, they compensate the negative bulk charge to give the turn‐around effect. The final C‐V curve is due to a complex sum of different charge components. The slow states can be discharged when heated under +5 V or higher biases at 160 °C or above. The final charge state is only semipermanent. Fast interface states are also annealed in the process, and the anneal is enhanced by a positive bias. Bulk trapped electrons are minimally perturbed by the anneal. It is postulated that the slow states may communicate with silicon through the fast interface states in a thermally activated process. In order to study bulk electron trapping, avalanche injection should be carried out at elevated temperatures.read more
Citations
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Journal ArticleDOI
Trap creation in silicon dioxide produced by hot electrons
D. J. DiMaria,James Stasiak +1 more
TL;DR: In this article, the authors show that trap creation in both the bulk of silicon dioxide films and at its interfaces with silicon and metallic contacting electrodes is dependent on the presence of hot electrons in the oxide.
Journal ArticleDOI
Interface trap generation in silicon dioxide when electrons are captured by trapped holes
TL;DR: In this article, a characteristic interface trap was observed in a hole trapping experiment when electrons were captured by trapped holes injected by an avalanche in the silicon, which could be explained by the generation of new electronic states through relaxation of strained bonds which were proposed to be the origin of hole traps.
Journal ArticleDOI
Effects of oxide traps, interface traps, and ‘‘border traps’’ on metal‐oxide‐semiconductor devices
Daniel M. Fleetwood,P.S. Winokur,R.A. Reber,T.L. Meisenheimer,J.R. Schwank,Marty R. Shaneyfelt,L.C. Riewe +6 more
TL;DR: In this article, a revised nomenclature for defects in MOS devices was developed, which clearly distinguishes the language used to describe the physical location of defects from that used to describing their electrical response.
Journal ArticleDOI
Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks
TL;DR: In this paper, the authors review various causes of threshold voltage instability in high/spl kappa/ gate dielectric stacks, including charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects.
Journal ArticleDOI
Border traps: issues for MOS radiation response and long-term reliability
Daniel M. Fleetwood,Marty R. Shaneyfelt,William L. Warren,J.R. Schwank,T.L. Meisenheimer,P.S. Winokur +5 more
TL;DR: In this article, the effects of border traps (near-interfacial oxide traps that can communicate with the underlying Si over a wide range of time scales) on the response of metal-oxide-semiconductor (MOS) devices to ionizing radiation are investigated.
References
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The si-sio, interface – electrical properties as determined by the metal-insulator-silicon conductance technique
E. H. Nicollian,A. Goetzberger +1 more
TL;DR: In this article, a realistic characterization of the Si-SiO 2 interface is developed, where a continuum of states is found across the band gap of the silicon, and the dominant contribution in the samples measured arises from a random distribution of surface charge.
Journal ArticleDOI
A quasi-static technique for MOS C-V and surface state measurements
TL;DR: In this paper, a quasi-static technique is proposed to obtain the thermal equilibrium MOS capacitance-voltage characteristics. The method is based on a measurement of the MOS charging current in response to a linear voltage ramp, so that the charging current is directly proportional to the incremental MOS capacity.
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Description of the SiO2Si interface properties by means of very low frequency MOS capacitance measurements
R. Castagné,A. Vapaille +1 more
TL;DR: In this paper, the authors measured the apparent interface density in the whole band gap of silicon and showed that the apparent inteiface density can contain a contribution of defects unspecific of the interface, for instance, spatial fluctuation of the interfaces or silicon defects introducing a deep level in the band gap.
Journal ArticleDOI
The effects of oxide traps on the MOS capacitance
F.P. Heiman,G. Warfield +1 more
TL;DR: In this paper, it is shown that the effective capture cross section of an oxide trap viewed by a carrier at the semiconductor surface is reduced by a factor which increases exponentially with the distance the trap is located from the interface.
Journal ArticleDOI
Electrochemical Charging of Thermal SiO2 Films by Injected Electron Currents
TL;DR: In this article, a series of experiments designed to characterize the charging effect of thermal SiO2 films with water was conducted. And they found that if water is diffused into a SiO 2 film, water related centers are formed which act like electron traps with capture cross section of approximately 1.5 × 10−17 cm2.