Level shifter design for low power applications
TLDR
Three new configurations of level shifters for low power application in 0.35{\mu}m technology have been presented and shows better performance in terms of power consumption with a little conciliation in delay.Abstract:
With scaling of Vt sub-threshold leakage power is increasing and expected to become significant part of total power consumption.In present work three new configurations of level shifters for low power application in 0.35µm technology have been presented. The proposed circuits utilize the merits of stacking technique with smaller leakage current and reduction in leakage power. Conventional level shifter has been improved by addition of three NMOS transistors, which shows total power consumption of 402.2264pW as compared to 0.49833nW with existing circuit. Single supply level shifter has been modified with addition of two NMOS transistors that gives total power consumption of 108.641pW as compared to 31.06nW. Another circuit, contention mitigated level shifter (CMLS) with three additional transistors shows total power consumption of 396.75pW as compared to 0.4937354nW. Three proposed circuit’s shows better performance in terms of power consumption with a little conciliation in delay. Output level of 3.3V has been obtained with input pulse of 1.6V for all proposed circuits.read more
Citations
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Journal ArticleDOI
Design of a Low Power Dissipation and Low Input Voltage Range Level Shifter in Cedec 0.18-µm Cmos Process
TL;DR: In this article, a low power dissipation and low input voltage range level shifter in CEDEC 0.18-µm CMOS process is presented, which fulfills the needs of lower power systems and will be very useful for ICs and SoCs.
Proceedings ArticleDOI
Design of voltage level shifter for multi-supply voltage design
Priti Gosatwar,Ujwala Ghodeswar +1 more
TL;DR: The proposed voltage level shifter converts low input voltage level into high level voltage output with increased speed and much less power consumption and has been implemented in a 90-nm BSIM4 level-54 CMOS technology.
Journal ArticleDOI
Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power Management
TL;DR: A hybrid voltage regulation solution, based on a charge-recycling off-chip voltage regulator and distributed integrated voltage regulators, to mitigate supply voltage noise effectively is proposed and the compatibility of VS with higher-level power management techniques is studied.
Journal ArticleDOI
A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter
TL;DR: The results of the simulations conducted using Cadence with standard 90-nm CMOS technology demonstrate the superiority of the proposed multiplier utilizing the proposed LC in terms of static and total power consumptions as well as power-delay product (PDP) as compared to the multipliers utilizing the previous level converters (LCs) and the single supply multiplier.
Proceedings ArticleDOI
Level shifter design for voltage stacking
TL;DR: This study explores different types of existing level shifters for voltage stacking application, their optimal sizing and energy, delay and area trade-offs, and includes effect the of PVT variation as another design factor and its impact on delay and energy consumption.
References
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