Journal ArticleDOI
Low Leakage Single Bitline 9T (SB9T) Static Random Access Memory
Reads0
Chats0
TLDR
This paper presents a low leakage, half-select free SB9T SRAM cell with good static and dynamic read/write performance along with smaller area that could be a good choice for applications that demand high stability, low power, low area and moderate speed.About:
This article is published in Microelectronics Journal.The article was published on 2017-04-01. It has received 54 citations till now. The article focuses on the topics: Static random-access memory.read more
Citations
More filters
Journal ArticleDOI
Robust TFET SRAM cell for ultra-low power IoT applications
TL;DR: The analysis and simulation results indicate that the proposed cell eliminates read disturb and outperforms the earlier 9T TFET bitcell in terms of static and dynamic write performance by using power cut-off and write-0 only technique.
Journal ArticleDOI
Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications
TL;DR: The proposed pseudo differential 12 transistor (PD12T) ultra-low leakage, fully half-select-free robust SRAM cell with good static and dynamic read/write performance and highest critical charge among all other considered cells is presented, which means that it is least vulnerable to soft-errors.
Journal ArticleDOI
Characterization of Half-Select Free Write Assist 9T SRAM Cell
TL;DR: The proposed HFWA9T cell has been compared with other contemporary designs such as feedback-cutting 7T (7T), fully differential 8T (FD8T), and single-ended disturb free 9T (SEDF9T) cells to analyze the impact of process variations on different design metrics.
Journal ArticleDOI
A highly stable reliable SRAM cell design for low power applications
TL;DR: The reliable nature of TG9T is indicated by the narrower spread in read stability, write ability, read delay and read current, as well as the lowest VDD,min among all SRAM bitcells used for comparison.
Journal ArticleDOI
A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications
Vishal Sharma,Maisagalla Gopal,Pooran Singh,Santosh Kumar Vishvakarma,Shailesh Singh Chouhan +4 more
TL;DR: In this paper, a data-dependent power-supply mechanism for a new 11T SRAM cell is proposed with ultra-low leakage and improved read/write stability against the process-voltage-temperature variations.
References
More filters
Proceedings ArticleDOI
Stable SRAM cell design for the 32 nm node and beyond
Leland Chang,David M. Fried,John M. Hergenrother,Jeffrey W. Sleight,R.H. Dennard,Robert K. Montoye,Lidija Sekaric,Sharee J. McNab,Anna W. Topol,C.D. Adams,Kathryn W. Guarini,Wilfried Haensch +11 more
TL;DR: This work demonstrates the smallest 6T and full 8T-SRAM cells to date and provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling.
Digital Integrated Circuits A Design Perspective
TL;DR: The digital integrated circuits a design perspective is universally compatible with any devices to read, and is available in the digital library an online access to it is set as public so you can get it instantly.
Journal ArticleDOI
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS
TL;DR: A differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability and provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC).
Journal ArticleDOI
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM
TL;DR: A novel Schmitt trigger (ST) based differential 10-transistor SRAM (static random access memory) bitcell suitable for subthreshold operation and does not require any architectural changes from the present 6T architecture is proposed.