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Quantum confinement induced performance enhancement in sub-5-nm lithographic Si nanowire transistors.

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TLDR
This study suggests simple (no additional doping) FETs using tiny top-down nanowires can deliver high performance for potential impact on both CMOS scaling and emerging applications such as biosensing.
Abstract
We demonstrate lithographically fabricated Si nanowire field effect transistors (FETs) with long Si nanowires of tiny cross sectional size (∼3-5 nm) exhibiting high performance without employing complementarily doped junctions or high channel doping. These nanowire FETs show high peak hole mobility (as high as over 1200 cm(2)/(V s)), current density, and drive current as well as low drain leakage current and high on/off ratio. Comparison of nanowire FETs with nanobelt FETs shows enhanced performance is a result of significant quantum confinement in these 3-5 nm wires. This study suggests simple (no additional doping) FETs using tiny top-down nanowires can deliver high performance for potential impact on both CMOS scaling and emerging applications such as biosensing.

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Citations
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Journal ArticleDOI

Semiconductor Nanowire Fabrication by Bottom-Up and Top-Down Paradigms

TL;DR: In this article, a range of routes to semiconductor nanowire production have opened up as a result of advances in nanowires fabrication techniques over the last number of decades.
Journal ArticleDOI

Effects of strain on the carrier mobility in silicon nanowires.

TL;DR: The results demonstrate that strain engineering can be used as a very efficient booster for NW technologies and that due care must be given to process-induced strains in NW devices to achieve reproducible performances.
Journal ArticleDOI

Room-Temperature Quantum Confinement Effects in Transport Properties of Ultrathin Si Nanowire Field-Effect Transistors

TL;DR: Electrical transport analysis for lithographically fabricated sub-5 nm thick Si nanowire field-effect transistors is presented and it is shown that confinement-induced quantum oscillations prevail at 300 K.
Journal ArticleDOI

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization

TL;DR: Aiming to provide a comprehensive roadmap for the development of SiNW FET based sensing platforms, this work critically review and discuss the key design and fabrication aspects relevant to their development and integration within complementary metal-oxide-semiconductor (CMOS) technology.
Journal ArticleDOI

Large-scale ordered 1D-nanomaterials arrays: Assembly or not?

TL;DR: In this paper, a review of the most recent developments in this field, with present perspective concerning their applicability as industrial processes, concentrating on the assembly of one-dimensional nanowires and nanotubes structures.
References
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Journal ArticleDOI

Nanowire Nanosensors for Highly Sensitive and Selective Detection of Biological and Chemical Species

TL;DR: The small size and capability of these semiconductor nanowires for sensitive, label-free, real-time detection of a wide range of chemical and biological species could be exploited in array-based screening and in vivo diagnostics.
Journal ArticleDOI

Chemistry and Physics in One Dimension: Synthesis and Properties of Nanowires and Nanotubes

TL;DR: In this article, the authors discuss the development of a general approach to rational synthesis of crystalline nanowires of arbitrary composition, and illustrate solutions to these challenges with measurements of the atomic structure and electronic properties of carbon nanotubes.
Journal ArticleDOI

High Performance Silicon Nanowire Field Effect Transistors

TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI

Nanowire transistors without junctions

TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Journal ArticleDOI

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
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